KSZ8995XA B3 Micrel Inc, KSZ8995XA B3 Datasheet - Page 19

• Manufacturer Part Number: KSZ8995XA B3
• Manufacturer: Micrel Inc

Specifications of KSZ8995XA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Micrel, Inc.
KS8995XA
Introduction
The KS8995XA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an
integrated Layer 2 switch. The device runs in three modes. The first mode is as a five-port integrated switch. The
second is as a five-port switch with the fifth port decoupled from the physical port. In this mode access to the fifth
MAC is provided through a media independent interface (MII) . This is useful for implementing an integrated
broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the
additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port.
The KS8995XA is optimized for an unmanaged design in which the configuration is achieved through I/O strapping or
EEPROM programming at system reset time.
On the media side, the KS8995XA supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and 100BASE-FX on
ports 4 and 5. The KS8995XA can be used as two separate media converters.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the
design more efficient and allows for lower power consumption and smaller chip die size.
The major enhancements from the KS8995E to the KS8995XA are support for programmable rate limiting, a dual MII
interface, MDC/MDIO control interface for IEEE 802.3-defined register configuration (not all the registers), per-port
broadcast storm protection, local loopback and lower power consumption.
The KS8995XA is pin-compatible to the managed switch, the KS8995M.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts
the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, and then
transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1
transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel conversion. The
receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to
adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes
itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as
temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by
the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the
MAC.
PLL Clock Synthesizer
The KS8995XA generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal.
Scrambler/De-Scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
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September 2008
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