KS8995XA B3 Micrel Inc, KS8995XA B3 Datasheet - Page 32

• Manufacturer Part Number: KS8995XA B3
• Manufacturer: Micrel Inc

Specifications of KS8995XA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

September 2008
Address
0
Register 4 (0x04): Global Control 2
7
6
5
4
3
2
1
Name
Aggressive back off
enable
Reserved
Multicast storm
protection disable
Reserved
Flow control and back
pressure fair mode
No excessive collision
drop
Huge packet support
Legal maximum packet
size check disable
Description
1, enable more aggressive back off algorithm in half
duplex mode to enhance performance. This is not an
IEEE standard.
Reserved
1, “Broadcast Storm Protection” does not include
multicast packets. Only DA=FFFFFFFFFFFF
packets will be regulated.
0, “Broadcast Storm Protection” includes DA =
FFFFFFFFFFFF and DA[40] = 1 packets.
Reserved
1, fair mode is selected. In this mode, if a flow
control port and a non-flow control port talk to the
same destination port, packets from the non-flow
control port may be dropped. This is to prevent the
flow control port from being flow controlled for an
extended period of time.
0, in this mode, if a flow control port and a non-flow
control port talk to the same destination port, the
flow control port will be flow controlled. This may not
be “fair” to the flow control port.
1, the switch will not drop packets when 16 or more
collisions occur.
0, the switch will drop packets when 16 or more
collisions occur.
1, will accept packet sizes up to 1916 bytes
(inclusive).
This bit setting will override setting from bit 1 of the
same register.
0, the max packet size will be determined by bit 1 of
this register.
1, will accept packet sizes up to 1536 bytes
(inclusive).
0, 1522 bytes for tagged packets (not including
packets with STPID from CPU to ports 1-4), 1518
bytes for untagged packets. Any packets larger than
the specified value will be dropped.
32
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Pin PMRXD0 strap
option. Pull-down
(0):
Disable aggressive
back off. Pull-up
(1): Aggressive
backoff. Note:
PMRXD0 has
internal pull-down.
Pin PMRXD1 strap
option. Pull-down
(0):
Drop excessive
collision packets.
Pull-up (1): Don’t
drop excessive
collision packets.
Note: PMRXD1 has
internal pull-down.
Pin PMRXER strap
option. Pull-down
(0):
1518/1522 byte
packets. Pull-up
value will be
dropped. (1): 1536
byte packets
Note: PMRXER
has internal pull-
down.
M9999-091508
Default
1
1
1
1
0