KS8995X-EVAL Micrel Inc, KS8995X-EVAL Datasheet

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KS8995X-EVAL

Manufacturer Part Number
KS8995X-EVAL
Description
BOARD EVAL EXPERIMENT KS8995X
Manufacturer
Micrel Inc
Type
Ethernetr
Datasheet
1.KS8995X-EVAL.pdf (4 pages)

Specifications of KS8995X-EVAL

Contents
Evaluation Board
For Use With/related Products
KS8995X
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
576-1021
Micrel Semiconductor
switch with optimized BOM (Bill-Of-Materials) cost for
low port count, cost-sensitive 10/100Mbps switch
systems. It also provides an extensive feature set including
three different QoS priority schemes, dual MII interface
for BOM cost reduction, programmable rate limiting to
offload CPU tasks, software & hardware power-down ,
MDC/MDIO control interface and port monitoring to
effectively address both current and emerging Fast
Ethernet applications.
patented mixed-signal low-power technology, five MAC
(Media Access Control) units, a high-speed non-blocking
switch fabric, a dedicated address lookup engine, and an
on-chip frame buffer memory.
In addition, two of the PHY units support 100BaseFX
(Ports 4 & 5).
Block Diagram
The KS8995X is a highly integrated layer-2 QoS
The KS8995X contains five 10/100 transceivers with
All PHY units support 10Base-T and 100BaseTX.
Integrated 5-Port 10/100 QoS Switch
TEL:
MII-SW or SNI
MDC, MDI/O
1.800.401.9572
MDI/MDIX
MDI/MDIX
MDI/MDIX
LED0[5:1]
LED1[5:1]
LED2[5:1]
MDI/MDIX
MDI/MDIX
Auto
Auto
Auto
Auto
MII-P5
Auto
T/Tx/Fx 4
T/Tx/Fx 5
LED I/F
10/100
10/100
10/100
10/100
10/100
T/Tx 1
T/Tx 2
T/Tx 3
FAX:
1.408.474.0159
Registers
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
Control
10/100
MAC 4
10/100
MAC 5
SNI
KS8995X Product Brief
Features
•
•
•
•
•
•
•
•
•
•
•
Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
Shared memory based switch fabric with fully non-
blocking configuration
10BaseT, 100BaseTX and 100BaseFX modes (FX
in Ports 4 & 5)
Dual MII configuration: MII-Switch (MAC or PHY
mode MII) and MII-P5 (PHY mode MII)
VLAN ID tag/untag options, per-port basis
Programmable rate limiting, ingress and egress port, rate
options for high and low priority, per port basis
Flow control or drop packet rate limiting (ingress port)
Broadcast storm protection with % control–global and
per-port basis
Optimization for fiber-to-copper media conversion
Full-chip hardware power-down support (register
configuration not saved)
Per-port based software power-save on PHY (idle link
detection, register configuration preserved)
HTTP://
www.micrel.com
1K look-up
EEPROM
Buffers
Engine
Queue
Mgmnt
Mgmnt
Frame
Buffer
I/F
Revision 1.08
1

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KS8995X-EVAL Summary of contents

Page 1

... Integrated 5-Port 10/100 QoS Switch The KS8995X is a highly integrated layer-2 QoS switch with optimized BOM (Bill-Of-Materials) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, dual MII interface for BOM cost reduction, programmable rate limiting to offload CPU tasks, software & ...

Page 2

Features • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per port basis (egress) • Port-based VLAN support • MDC and MDI/O interface support to access the MII PHY control ...

Page 3

System Level Applications CPU WAN PHY & AFE (xDSL, CM...) Micrel Semiconductor 1.800.401.9572 TEL: 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC External WAN port PHY ...

Page 4

Contact Micrel Semiconductor Location Address Corporate HQ 1849 Fortune Drive Eastern USA 93 Branch Street Southeast USA 8105 Bluffridge Drive Central USA 722 S. Denton Tap Suite 130 Western USA 2180 Fortune Drive Northwest USA 401 NE Ravenna Blvd. Box ...

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