CLC018AJVJQ National Semiconductor, CLC018AJVJQ Datasheet - Page 10

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CLC018AJVJQ

Manufacturer Part Number
CLC018AJVJQ
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of CLC018AJVJQ

Number Of Arrays
1
Differential Data Transmission
Yes
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Cascading Capability
No
Line Code
NRZ
On-chip Buffers
No
On-chip Mux/demux
No
Lead Free Status / RoHS Status
Not Compliant

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Supply Operation
I/O Data Level
Control Signal Low/High
Connection
Key Information
Operation
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports in a switch array, the
inputs of multiple CLC018s are connected in parallel. The
bus used to connect the input ports should be a controlled
impedance transmission line as shown in Figure 11. To
(Continued)
TABLE 1. Interfacing of the Power Supplies and Bypass Capacitors
1. Bypass each V
with a 0.01 µF capacitor. 2.
Connect V
ground plane. 3. A power
plane isn’t required for V
but can be used.
Single −5V
−5V/GND
CC
ECL
and V
EE
LL
supply
to the
EE
1. Bypass each V
a 0.01 µF capacitor. 2. Bypass
the V
3. Connect V
plane. 4. Use a +5V power
plane for V
10
LL
control the switch array, the IA, OA and TRI busses are all
connected in parallel and a decoder is used to assert high
the CS of the CLC018 that is to be addressed. This is also
shown in Figure 11.
supply with a 0.01 µF.
Single +5V
CC
GND/+5V
EE
PECL
.
to the ground
CC
supply with
1. Bypass each V
with a 0.01 µF capacitor. 2.
Bypass the V
0.01 µF. 3. Connect V
the ground plane. 4. A power
plane isn’t required for +5V
(V
but can be used.
LL
) or −5V (V
Dual
GND/+5V
ECL
LL
EE
±
supply with a
5V
EE
) supplies.
supply
CC
to

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