HS1-82C54RH-Q Intersil, HS1-82C54RH-Q Datasheet - Page 15

• Manufacturer Part Number: HS1-82C54RH-Q
• Manufacturer: Intersil
• Type: Programmabler

Specifications of HS1-82C54RH-Q

• # Internal Timers: 1
• Operating Supply Voltage (typ): 5V
• Package Type: SBDIP
• Pin Count: 24
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Compliant

NOTES:
54. Counters are programmed for binary (not BCD) counting and for
55. The Counter is always selected (CS always low).
56. CW stands for “Control Word”; CW = 10 means a Control Word
57. LSB stands for “Least significant byte” of count.
58. Numbers below diagrams are count values. The lower number is
59. N stands for an undefined count.
60. Vertical lines show transitions between count values.
GATE
GATE
GATE
OUT
OUT
OUT
CLK
CLK
CLK
reading/writing least significant byte (LSB) only.
of 10, Hex is written to the Counter.
the least significant byte. The upper number is the most
significant byte. Since the Counter is programmed to read/write
LSB only, the most significant byte cannot be read.
WR
WR
WR
SIGNAL STATUS MODES
CW = 1A LSB = 3
CW = 1A LSB = 3
CW = 1A LSB = 3
N
N
N
N
N
N
0
1
2
3
4
5
N
N
N
FIGURE 22. MODE 5
N
N
N
N
N
N
LSB = 5
N
0
3
0
3
15
0
2
0
3
0
2
Disables counting
1) Disables counting
2) Sets output immediately high
1) Disables counting
2) Sets output immediately high
1) Disables counting
0
1
0
2
0
1
0
0
0
3
0
0
LOW OR GOING LOW
FF
FF
FF
FF
0
2
FF
FE
0
3
0
1
GATE PIN OPERATIONS SUMMARY
-
-
0
0
0
5
FF
FF
0
4
HS-82C54RH
Operation Common to All Modes
Programming
When a Control Word is written to a Counter, all Control
Logic is immediately reset and OUT goes to a known initial
state; no CLK pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of CLK.
In Modes 0, 2, 3 and 4 the GATE input is level sensitive, and
logic level is sampled on the rising edge of CLK. In modes 1, 2,
3 and 5 the GATE input is rising-edge sensitive. In these
Modes, a rising edge of Gate (trigger) sets an edge-sensitive
flip-flop in the Counter. This flip-flop is then sampled on the next
rising edge of CLK. The flip-flop is reset immediately after it is
sampled. In this way, a trigger will be detected no matter when it
occurs - a high logic level does not have to be maintained until
the next rising edge of CLK. Note that in Modes 2 and 3, the
GATE input is both edge-and level-sensitive.
Counter
New counts are loaded and Counters are decremented on
the falling edge of CLK.
The largest possible initial count is 0; this is equivalent to 2
for binary counting and 10
The Counter does not stop when it reaches zero. In Modes
0, 1, 4 and 5 the Counter “wraps around” to the highest
count, either FFFF hex for binary counting or 9999 for BCD
counting, and continues counting. Modes 2 and 3 are
periodic; the Counter reloads itself with the initial count and
continues counting from there.
NOTE: 0 is equivalent to 2
counting.
1) Initiates counting
2) Resets output after next clock
Initiates counting
Initiates counting
Initiates counting
MODE
0
1
2
3
4
5
MINIMUM AND MAXIMUM INITIAL COUNTS
RISING
-
-
16
MIN COUNT
4
for binary counting and 10
for BCD counting.
1
1
2
2
1
1
Enables counting
Enables counting
Enables counting
Enables counting
MAX COUNT
HIGH
-
-
4
0
0
0
0
0
0
for BCD
16