HS1-3282-8 Intersil, HS1-3282-8 Datasheet
HS1-3282-8
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HS1-3282-8 Summary of contents
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... Generate Parity of Transmitter Data • Automatic Word Gap Timer • Single 5V Supply • Low Power Dissipation • Full Military Temperature Range Ordering Information PACKAGE TEMP. RANGE PART NUMBER o o CERDIP - +125 C HS1-3282-8 SMD# 5962-8688001QA o o CLCC - +85 C HS4-3282- - +125 C HS4-3282-8 ...
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Pinouts D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 HS-3282 HS-3282 (CERDIP) TOP VIEW 429DI1( 429DI1( CLK 429DI2( CLK 429DI2( D/R1 6 ...
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Pin Description PIN SYMBOL SECTION 1 V Recs/Trans CC 2 429 DI1 (A) Receiver 3 429 DI1 (B) Receiver 4 429 Dl2 (A) Receiver 5 429 DI2 (B) Receiver 6 D/R1 Receiver 7 D/R2 Receiver 8 SEL Receiver 9 EN1 ...
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Pin Description (Continued) PIN SYMBOL SECTION 31 429D0 Transmitter 32 429D0 Transmitter 33 ENTX Transmitter 34 CWSTR Recs/Trans CLK Recs/Trans 38 TXCLK Transmitter 39 MR Recs/Trans Pinout ...
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Operational Description The HS-3282 is designed to support ARINC Specification 429 and other serial data protocols that use a similar format by collecting the receiving, transmitting, synchronizing, timing and parity functions on a single, low power LSl circuit. It goes ...
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TABLE 2B. WORD 2 FORMAT BI-DIRECTIONAL BlT# FUNCTION 15 Sign 14 MSB Data Receiver Parity Status Odd Parity 1 = Even Parity If the receiver input data word string is broken before the entire data ...
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Transmitter Operation The Transmitter section consists of an 8-word deep by 31- Bit long FIFO Memory, Parity Generator, Transmitter Word Gap Timing Circuit and Driver Circuit. • The FlFO Memory is organized in such a way that data loaded in ...
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WLSEL SELF TEST 429D11 (A) 2 SEL LINE RECEIV. 429D11 ( SLF TEST S/DENB S/D WDCNT 1 DECODER WDCNT 2 S/D CODER 429D12 (A) 4 LINE RECEIV. 429D12 ( SEL SELF TEST WLSEL RCV ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Performance Specifications PARAMETER Clock Frequency Data Rate 1/ Data Rate 2/ Master Reset Pulse Width RECEIVER TIMING Receiver Ready Time From 32nd Bit 1/ Receiver Ready Time From 32nd Bit 2/ Device Ready to Enable Time Data Enable ...
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AC Electrical Performance Specifications PARAMETER Data Word Gap Time 1/ Data Word Gap Time 2/ Data Transmission Word to TX/R Set Time Enable Transmit Turnoff Time REPEATER OPERATION TIMING Data Enable to Parallel Load Delay Time Data Enable Hold for ...
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Timing Waveforms TX/R TX ENABLE DATA BUS PL1 PL2 D/R1 D/R2 EN1 EN2 SEL TIME INTERVAL A BUS IS BEING USED AS AN OUTPUT FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE 429DI BIT 32 t D/R D/R EN SEL BD00-15 SEL ...
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Timing Waveforms (Continued) CWSTR BD00-15 PL1 t PL PL2 TX/R t DWSET BD00-15 WORD 1 TX/R ENTX t ENDAT BIT 42900 1 HS-3282 t CWSTR t CWHLD t CWSET CONTROL WORD FIGURE 4. CONTROL WORD TIMING t PL12 t PL ...
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Timing Waveforms (Continued) 429DI BIT 32 t D/R D/R t D/REN EN t SELEN SEL t ENPL PL1 PL2 TX/R ENTX 429D0 HS-3282 t END/R t ENEN SELEN t t ENSEL ENSEL t PLEN t ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Burn-In Circuits F15 F14 F13 F12 F11 NOTES: 1. Resistors = 47kΩ, 5%, 1/4W (Min) 2. GND = Ground = +5.5V, ±0. 0.01mF/Socket (Min ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...