PCKEP14D-T NXP Semiconductors, PCKEP14D-T Datasheet - Page 2

• Manufacturer Part Number: PCKEP14D-T
• Description: Clock Synthesizer / Jitter Cleaner 2.5/3.3V 1:5 ECL/PECL/HSTL CLK
• Manufacturer: NXP Semiconductors
• Type: Clock Driverr

Specifications of PCKEP14D-T

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: >2000MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/HSTL/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 20
• Mounting Style: SMD/SMT
• Package / Case: SO-20
• Lead Free Status / RoHS Status: Compliant
• Other names: PCKEP14D,118

Philips Semiconductors
3. Pinning information
9397 750 09565
Product data
3.2.1 Power supply connection
3.1 Pinning
3.2 Pin description
Table 1:
Symbol
Q0-Q4
Q0-Q4
V
CLK_SEL
CLK0, CLK1
CLK0, CLK1
V
V
EN
CAUTION
Fig 1. SO20 pin configuration.
EE
BB
CC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Pin description
10
1
2
3
4
5
6
7
8
9
MSC895
Pin
1, 3, 5, 7, 9
2, 4, 6, 8, 10
11
12
13, 16
14, 17
15
18, 20
19
Rev. 01 — 30 October 2002
002aaa354
All V
proper operation.
20
19
18
17
16
15
14
13
12
11
CC
2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver
V CC
EN
V CC
CLK1
CLK1
V BB
CLK0
CLK0
CLK_SEL
V EE
and V
Description
Positive ECL/PECL output
Negative ECL/PECL output
Negative supply
ECL/PECL active clock select input. Pin will default LOW
when left open.
ECL/PECL/HSTL CLK input. Pins will default LOW when
left open.
ECL/PECL/HSTL CLK input. Pins will default to V
left open.
Reference voltage output
Positive supply
ECL synchronous enable
EE
pins must be connected to power supply to guarantee
Fig 2. TSSOP20 pin configuration.
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
10
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
1
2
3
4
5
6
7
8
9
002aaa221
PCKEP14
20
19
18
17
16
15
14
13
12
11
V CC
EN
V CC
CLK1
CLK1
V BB
CLK0
CLK0
CLK_SEL
V EE
CC
/2 when
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