XC3S250E-4FT256C Xilinx Inc, XC3S250E-4FT256C Datasheet - Page 86

• Manufacturer Part Number: XC3S250E-4FT256C
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S250E-4FT256C

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 221184

Functional Description
determines how the FPGA generates addresses, as shown
Table
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
86
A
During configuration, the value of the M0 mode pin
58. When M0 = 0, the FPGA generates addresses
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
Recommend
open-drain
PROG_B
driver
TMS
TDO
TCK
TDI
+2.5V
JTAG
Not available
in VQ100
package
BPI Mode
‘0’
‘1’
‘0’
‘0’
P
A
HSWAP
M2
M1
M0
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Spartan-3E
FPGA
VCCINT
+1.2V
GND
www.xilinx.com
VCCAUX
VCCO_1
VCCO_0
VCCO_2
A[23:17]
CSO_B
A[16:0]
INIT_B
DONE
BUSY
CCLK
LDC0
LDC1
LDC2
D[7:0]
HDC
TDO
Table 58: BPI Addressing Control
M2
0
VCCO_0
M1
+2.5V
V
V
1
V
M0
0
1
I
Start Address
0xFF_FFFF
0
CE#
OE#
WE#
BYTE#
DQ[15:7]
DQ[7:0]
A[n:0]
DS312-2 (v3.8) August 26, 2009
DS312-2_49_082009
VCCO
GND
V
x8/x16
PROM
Flash
x8 or
+2.5V
D
Product Specification
Incrementing
Decrementing
Addressing
R