XC95144XL-10CS144I Xilinx Inc, XC95144XL-10CS144I Datasheet - Page 7

• Manufacturer Part Number: XC95144XL-10CS144I
• Description: CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC95144XL-10CS144I

• Package: 144CSBGA
• Family Name: XC9500XL
• Device System Gates: 3200
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 117
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C

Product Term Allocator
The product term allocator controls how the five direct prod-
uct terms are assigned to each macrocell. For example, all
five direct terms can drive the OR function as shown in
Figure
The product term allocator can re-assign other product
terms within the FB to increase the logic capacity of a mac-
rocell beyond five direct terms. Any macrocell requiring
additional product terms can access uncommitted product
terms in other macrocells within the FB. Up to 15 product
terms can be available to a single macrocell with only a
small incremental delay of t
DS054 (v2.5) May 22, 2009
Product Specification
Figure 5: Macrocell Logic Using Direct Product Term
5.
R
Product Term
Allocator
PTA
,
as shown in
Macrocell
Product Term
Logic
DS054_05_042101
Figure
6.
www.xilinx.com
Note that the incremental delay affects only the product
terms in other macrocells. The timing of the direct product
terms is not changed.
XC9500XL High-Performance CPLD Family Data Sheet
Figure 6: Product Term Allocation With 15 Product
Product Term
Allocator
Product Term
Product Term
Allocator
Allocator
Terms
Macrocell Logic
With 15
Product Terms
DS054_06_042101
7