72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 5

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

TABLE 1 — BUS-MATCHING CONFIGURATION MODES
NOTE:
1. Pin status during Master Reset.
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
BM
H
H
H
H
L
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
(x72, x36, x18) DATA IN (D
FIRST WORD FALL THROUGH/
WRITE CHIP SELECT (WCS)
WRITE CLOCK (WCLK/WR)
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
I W
H
H
L
L
L
Figure 1. Single Device Configuration Signal Flow Diagram
PARTIAL RESET (PRS)
INPUT WIDTH (IW)
LOAD (LD)
0
- D
n
)
OW
H
H
L
L
L
MATCHING
72T72105
72T72115
72T7285
72T7295
(BM)
BUS-
IDT
5
MASTER RESET (MRS)
OUTPUT WIDTH (OW)
REN ECHO, EREN
RCLK ECHO, ERCLK
RETRANSMIT (RT)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
(x72, x36, x18) DATA OUT (Q
MARK
EMPTY FLAG/OUTPUT READY (EF/OR)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
OUTPUT ENABLE (OE)
READ CHIP SELECT (RCS)
Write Port Width
x72
x72
x72
x36
x18
COMMERCIAL AND INDUSTRIAL
0
- Q
TEMPERATURE RANGES
Read Port Width
n
)
5994 drw03
x72
x36
x18
x72
x72