MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 54

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 38:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
COMMAND
A0–A9, A11
Precharge all
DQM /
BA0, BA1
active banks
CKE
CLK
A10
DQ
Power-Down Mode
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
Notes:
BANK(S)
T0
t CKH
t CMH
t AH
1. Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
54
Exit power-down mode
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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128Mb: x4, x8, x16 SDRAM
t CKS
Tn + 1
NOP
All banks idle
©1999 Micron Technology, Inc. All rights reserved.
Timing Diagrams
Tn + 2
ACTIVE
ROW
ROW
BANK
DON’T CARE