MT46V128M8P-6T:A Micron Technology Inc, MT46V128M8P-6T:A Datasheet - Page 30
![DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V128M8P-6T:A
Manufacturer Part Number
MT46V128M8P-6T:A
Description
DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V128M8P-6T:A
Density
1 Gb
Maximum Clock Rate
333 MHz
Package
66TSOP
Address Bus Width
16 Bit
Operating Supply Voltage
2.5 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (128M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Package / Case
66-TSOP
Organization
128Mx8
Address Bus
16b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
230mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 13:
Figure 14:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Reduced Drive Pull-Down Characteristics
Reduced Drive Pull-Up Characteristics
40. The voltage levels used are derived from a minimum V
41.
42. V
43.
39d. The driver pull-up current variation, within nominal voltage and temperature
39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should
39f. The full ratio variation of the nominal pull-up to pull-down current should be
80
70
60
50
40
30
20
10
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
V
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) =
for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle
rate.
t
prevail over
HZ (MAX) will prevail over
0
-10
-20
-30
-40
-50
-60
-70
-80
IH
DD
0 . 0
0
0.0
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 14 on page 30.
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
overshoot: V
and V
DD
0 . 5
t
0.5
DQSCK (MIN) +
Q must track each other.
IH
(MAX) = V
1 . 0
1.0
V
DD
V
Q - V
OUT
30
t
(V)
OUT
DQSCK (MAX) +
t
RPRE (MAX) condition.
DD
(V)
1 . 5
1.5
Q + 1.5V for a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – DC and AC
2.0
2.0
t
RPST (MAX) condition.
pulse width ≤ 3ns, and the pulse
1Gb: x4, x8, x16 DDR SDRAM
2.5
2.5
DD
level and the referenced test
©2003 Micron Technology, Inc. All rights reserved.
t
LZ (MIN) will
–
1.5V