MT46H32M16LFBF-6 IT:C Micron Technology Inc, MT46H32M16LFBF-6 IT:C Datasheet - Page 37
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MT46H32M16LFBF-6 IT:C
Manufacturer Part Number
MT46H32M16LFBF-6 IT:C
Description
DRAM CHIP DDR SDRAM 512MBIT 1.8V 60VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H32M16LFBF-6_ITC.pdf
(95 pages)
Specifications of MT46H32M16LFBF-6 IT:C
Lead Free Status / Rohs Status
Compliant
- Current page: 37 of 95
- Download datasheet (4Mb)
Figure 10: READ Command
WRITE
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. C 1/11 EN
Note:
BA0, BA1
The WRITE command is used to initiate a burst write access to an active row. The val-
ues on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0]
(where I = the most significant column address bit for each configuration) selects the
starting column location. The value on input A10 determines whether auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the WRITE burst; if auto precharge is not selected, the row will remain open for subse-
quent accesses. Input data appearing on the DQ is written to the memory array, subject
to the DM input logic level appearing coincident with the data. If a given DM signal is
registered LOW, the corresponding data will be written to memory; if the DM signal is
registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to
stopping the clock (see Clock Change Frequency (page 94)). A burst completion for
WRITEs is defined when the write postamble and
Address
1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
CAS#
RAS#
WE#
A10
CK#
CKE
CS#
CK
HIGH
Column
EN AP
DIS AP
Bank
Don’t Care
37
512Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WR or
t
WTR are satisfied.
© 2009 Micron Technology, Inc. All rights reserved.
Commands
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