74LVC125APW-T NXP Semiconductors, 74LVC125APW-T Datasheet - Page 9

• Manufacturer Part Number: 74LVC125APW-T
• Description: Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin TSSOP T/R
• Manufacturer: NXP Semiconductors

Specifications of 74LVC125APW-T

• Package: 14TSSOP
• Logic Family: LVC
• Logic Function: Buffer/Line Driver
• Number Of Outputs Per Chip: 4
• Output Type: 3-State
• Input Signal Type: Single-Ended
• Maximum Propagation Delay Time @ Maximum Cl: 2.4(Typ)@3.3V ns
• Tolerant I/os: 5 V
• Typical Quiescent Current: 0.1 uA
• Polarity: Non-Inverting

Philips Semiconductors
AC WAVEFORMS
2003 May 07
handbook, full pagewidth
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
V
V
V
V
V
V
V
V
V
M
M
OL
M
M
X
X
Y
Y
= V
= V
= V
= V
= 1.5 V at V
= 0.5V
= 1.5 V at V
= 0.5V
and V
OL
OL
OH
OH
+ 0.3 V at V
+ 0.1 V at V
+ 0.3 V at V
+ 0.1 V at V
CC
CC
OH
at V
at V
are typical output voltage drop that occur with the output load.
CC
CC
CC
CC
< 2.7 V;
< 2.7 V;
2.7 V;
2.7 V;
CC
CC
CC
CC
< 2.7 V;
< 2.7 V.
2.7 V;
2.7 V;
HIGH-to-OFF
OFF-to-HIGH
OFF-to-LOW
LOW-to-OFF
nOE input
output
output
handbook, halfpage
Fig.6 The input nA to output nY propagation delays.
V
OL
nY output
nA input
and V
GND
GND
V OH
V CC
V OL
V I
Fig.7 3-state enable and disable times.
OH
GND
are typical output voltage drop that occur with the output load.
V OH
V OL
V I
V M
enabled
outputs
t PLZ
t PHZ
V M
V X
9
V M
V Y
t PHL
disabled
outputs
t PZL
t PZH
MNA230
t PLH
V M
V M
outputs
enabled
MNA362
Product specification
74LVC125A