HCTL-2017-PLC Avago Technologies US Inc., HCTL-2017-PLC Datasheet - Page 9

• Manufacturer Part Number: HCTL-2017-PLC
• Description: Quadrature Decoder/Counter Interface IC 16-Pin PDIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2017-PLC

• Package: 16PDIP
• Operating Temperature: -40 to 85 °C
• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 20-PLCC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-1882-5; HCTL-2017-PLC

Position Data Latch
The position data latch is a 16-bit latch which captures
the position counter output data on each rising clock
edge, except when its inputs are disabled by the inhibit
logic section during four-byte read operations. The
output data is passed to the bus interface section. When
active, a signal from the inhibit logic section prevents
new data from being captured by the latch, keeping
the data stable while successive reads are made through
the bus section. The latch is automatically re-enabled
at the end of these reads. The latch is cleared to 0
asynchronously by the RST signal.
Inhibit Logic
The Inhibit Logic Section samples the OE and SEL signals
on the falling edge of the clock and, in response to
certain conditions (see Figure 10), inhibits the position
data latch. The RST signal asynchronously clears the
inhibit logic, enabling the latch.
Bus Interface
The bus interface section consists of a 16 to 8 line
multiplexer and an 8-bit, three-state output buffer. The
multiplexer allows independent access to the low and
high bytes of the position data latch. The SEL and OE
signals determine which byte is output and whether or
not the output bus is in the high-Z state.
Figure 11. Simplified Inhibit Logic
9
Figure 10. Two Bytes Read Sequence
Step
1
2
3
SEL
L
H
X
OE
L
L
H
Falling
Falling
Falling
CLK
Quadrature Decoder Output
The quadrature decoder output section consists of
count and up/down outputs derived from the 4x
decoder mode of the HCTL-2021/2017. When the
decoder has detected a count, a pulse, one-half clock
cycle long, will be output on the CNT
output will occur during the clock cycle in which the
internal counter is updated. The U/D pin will be set to
the proper voltage level one clock cycle before the rising
edge of the CNT
after the rising edge of the CNT
outputs are not affected by the inhibit logic.
Cascade Output
The cascade output also consists of count and up/down
outputs. When the HCTL-2021/2017 internal counter
overflows or underflows, a pulse, one-half clock cycle
long, will be output on the CNT
occur during the clock cycle in which the internal
counter is updated. The U/D pin will be set to the proper
voltage level one clock cycle before the rising edge of
the CNT
rising edge of the CNT
affected by the inhibit logic.
1
1
Inhibit Signal
0
CAS
pulse, and held one clock cycle after the
DCDR
CAS
pulse, and held one clock cycle
Set inhibit; read high byte
Read low byte; starts reset
Complete inhibit logic reset
Action
pulse. These outputs are not
CA
S pin. This output will
DCDR
DCDR
pulse. These
pin. This