BOXD510MO Intel (CPU), BOXD510MO Datasheet - Page 19

• Manufacturer Part Number: BOXD510MO
• Manufacturer: Intel (CPU)

Specifications of BOXD510MO

• Lead Free Status / RoHS Status: Supplier Unconfirmed

1.5.2
1.5.3
The board provides up to seven USB 2.0 ports, supports UHCI and EHCI, and uses
UHCI- and EHCI-compatible drivers. The port arrangement is as follows:
•
•
NOTE
One of the front panel USB headers supports an Intel Z-U130 USB Solid-State Drive
(or compatible device).
Computer systems that have an unshielded cable attached to a USB port may not
meet FCC Class B requirements, even if no device is attached to the cable. Use
shielded cable that meets the requirements for full-speed devices.
The board provides two SATA interface connectors that support one device per
connector.
The board’s SATA controller offers independent SATA ports with a theoretical
maximum transfer rate of 3.0 Gbits/sec on each port. One device can be installed on
each port for a maximum of two SATA devices. A point-to-point interface is used for
host to device connections, unlike PATA which supports a master/slave configuration
and two devices on each channel.
For compatibility, the underlying SATA functionality is transparent to the operating
system. The SATA controller supports IDE and AHCI configuration and can operate in
both legacy and native modes. In legacy mode, standard ATA I/O and IRQ resources
are assigned (IRQ 14 and 15). In Native mode, standard PCI Conventional bus
resource steering is used. Native mode is the preferred mode for configurations using
the Windows* XP and Windows Vista* operating systems.
For information about
The location of the USB connectors on the back panel
The location of the front panel USB headers
For information about
Obtaining AHCI driver
The location of the SATA connectors
Four ports are implemented with stacked back panel connectors
Three front panel ports (via two internal headers; one header (with one port)
supports an Intel
USB
SATA Support
®
Z-U130 USB Solid-State Drive (or compatible device)
Refer to
Figure 8, page 39
Figure 10, page 41
Refer to
Section 1.2, page 14
Figure 10, page 41
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