SCANSTAEVK/NOPB National Semiconductor, SCANSTAEVK/NOPB Datasheet - Page 22

• Manufacturer Part Number: SCANSTAEVK/NOPB
• Manufacturer: National Semiconductor

Specifications of SCANSTAEVK/NOPB

• Lead Free Status / RoHS Status: Compliant

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Special Features
registers (one register per LSP). The GPIO outouts are
updated during the UPDATE-DR state and the GPIO input
values are written to the corresponding GPIO register during
the CAPTURE-DR state.
LSP SHARED: In the shared mode of opeartion, the dot1
LSP pins TDI
TMS
mode.
The sequence of operations to use shared GPIOs on an LSP
are as follows (example uses LSP
1. IR-Scan the STA111 address into the instruction register
2. IR-Scan the MODESEL
3. DR-Scan 00000001 into Mode Register
4. IR-Scan the SGPIO
5. DR-Scan 00000011 into the Shared GPIO Register
6. Step 5 can be repeated to generate waveforms on TDO
7. IR-Scan the GOTOWAIT or SOFTRESET instruction, or
ADDRESS INTERROGATION
The STA111 has four states that it can goto from the Wait-
For-Address state: Unselected, Singularly-selected, Multi/
Broadcast-selected, and Address-interrogation (see Figure
13).
After a reset (or GOTOWAIT command) has been issued,
the STA111 TAP is sequenced to the Capture-IR state where
XXXXXX01 is loaded into the shift register. Upon entering
the Shift-IR state, the instruction register is filled with the
address interrogation value (3A hex) which is loaded into the
address register as the TAP is sequenced into the Update-IR
state. On the next loop through Capture-IR the shift register
is loaded with the ones-complement of the slot address. In
the Shift-IR state the address interrogation value is loaded
into the instruction register. The value presented on TDO
will be a wired-and address of all of the STA111s on the bus.
As this value is being shifted out, each STA111 will monitor
its TDO
If the device shifts all bits of its ones-complement address
and never gets a compare error it will tri-state TDO
to the Wait-For-Reset state. Alternately, if the device sees a
compare error while it is shifting its ones-complement ad-
dress it will stop shifting its address and tri-state TDO
(address a STA111).
register to select Mode Register
ration register) as the data register.
GPIOs on LSP
TAP enters the RTI state at the end of this shift operation
(TDO
the default value in the Shared GPIO Register
ister to select the Shared GPIO Register
register.
set TDO
Update-DR). During this operation, when the TAP enters
Capture-DR, the present value on the TDI
values of TDO
Register
register and will be scanned out 00000X00 (X = value
present on TDI
and TMS
data, TDO
TAP state = Update-DR) and 00000X11 would be
scanned out (X = value present on TDI
enters Capture-DR).
generate a TRST
n
and TDO
B
to see if it is receiving the same value it is driving.
0
and TMS
0
0
) will be captured into bits 2, 1 and 0 of the shift
0
n
. If step 5 was repeated with 00000000 as
0
, TDO
and TMS
n
and TMS
are outputs, TDI
0
0
0
. The GPIOs will be enabled when the
0
when TAP enters Capture-DR).
n
B
and TMS
will be forced to logic 0 as defined by
and TMS
reset to disable the GPIOs.
0
0
instruction into the instruction reg-
0
to a logic 1 (when TAP enters
would be set to a logic 0 (when
3
instruction into the instruction
(Continued)
0
n
(as set by Shared GPIO
n
pins become GPIO pins.
0
):
3
is an input in the GPIO
(Shared GPIO configu-
0
0
0
3
as the data
pin and the
when TAP
to enable
0
B
).
and go
B
until
0
to
B
0
22
the next shift operation; during the next Shift-IR operation it
will again try to present its address (if the previous instruction
was 3A hex) while monitoring TDO
Shifting 3A hex into the instruction registers of the STA111s
will continue until all STA111s have presented their address.
At this time all devices will be waiting to be reset, and if a 3A
is shifted into the STA111 instruction registers the address
read by the tester will be all weak 1s due to all TDO
tri-stated. Reading all ones will signal the tester that address
interrogation is complete. Since all ones signifies the end of
Address-Interrogation, no device can have an address of all
zeros (ones-complement).
If at any time, during the address interrogation mode, any
other instruction besides 3A hex is shifted into the instruction
register, then the STA111 will exit the interrogation mode.
Also, the STA111’s state machine will go to the Wait-For-
Address state.
This address interrogation scheme presumes that TDO
capable of driving a weak 1 and that an STA111 driving a 0
will overdrive an STA111 driving a weak 1.
The following is an example of the Address-Interrogation
function. Assume there are three STA111s (U1, U2 and U3)
on a dot1 backplane with slot addresses 010100, 100000
and 000001 respectively (assuming 6 address pins).
1. The STA111s are reset and the interrogation address/
2. At the end of the instruction shift (Update-IR) the STA111
3. The TAPs are sequenced to Capture-IR and the shift
4. The TAPs are sequenced to Shift-IR and the LSB of the
5. The weak 1 being driven on U1 and U2 is overdriven by
6. The shift operation continues and U3 finishes shifting its
7. The TAPs are again sequenced to Capture-IR and U1
8. The TAPs are sequenced to Shift-IR and the LSB of the
9. Since both U1 and U2 are driving a weak 1 the shift
10. Again U1 and U2 drive weak 1 and the shift continues.
11. U2s weak 1 is overdriven by U1s 0 and U2 enters the
12. The shift operation continues and U1 finishes shifting its
13. The instruction shift operation is repeated and U2 shifts
14. The instruction shift operation is repeated, however, all
op-code (3A hex) is shifted into the instruction registers.
address registers are loaded with 3A hex.
registers latch the ones-complement slot addresses
(U1=101011, U2=011111 and U3=111110).
interrogation address is presented on the TDI
currently, the LSBs of the ones-complement slot ad-
dresses are presented on the respective TDO
the 0 from U3. U1 and U2 enter the Wait-For-Next-
Interrogation state.
ones-complement address (111110) out on TDO
enters the Wait-For-Reset state when the TAP enters
Update-IR.
and U2 shift registers latch the ones-complement ad-
dresses (U1=101011, U2=011111).
interrogation address is presented on the TDI
currently, the LSBs of the ones-complement addresses
are presented on the respective TDO
continues.
Wait-For-Next-Interrogation state.
ones-complement address (101011) out on TDO
enters theWait-For-Reset state.
its ones-complement address (011111) out on TDO
enters the Wait-For-Reset state.
devices have been interrogated and are waiting for a
reset. The master device will receive all ones. This
implies that there can not be an STA111 with address 0!
B
.
B
’s.
B
B
B
B
’s.
’s. Con-
’s. Con-
’s being
B
B
B
. U3
. U1
. U2
B
is