M54455EVB Freescale, M54455EVB Datasheet - Page 23

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.13.1.1
4.13.1.2
Freescale Semiconductor
Q
Field
Field
31–6
31–6
SW7
SW6
SW7
SW6
3–0
PCI
3–0
PCI
Address: 0x0900_0000 (FPGA_IRQEN)
Address: 0x0900_0004 (FPGA_IRQSTATUS)
5
4
5
4
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
W
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW7 SW6
Reserved, must be cleared.
Setting this bit allows the SW7 pushbutton interrupt source to be passed through to the IRQ line determined by
FPGA_IRQROUTE.
1 SW7 interrupt is enabled
0 SW7 interrupt source does not assert an IRQ
Setting this bit allows the SW6 pushbutton interrupt source to be passed through to the IRQ line determined by
FPGA_IRQROUTE.
1 SW6 interrupt is enabled
0 SW6 interrupt source does not assert an IRQ
Setting these bits allow the corresponding PCI interrupt source to be passed through to the IRQ line determined by
FPGA_IRQROUTE.
1 Corresponding PCI interrupt is enabled
0 Corresponding PCI interrupt source does not assert an IRQ
Reserved, must be cleared.
Indicates the SW7_b signal is asserted. This bit shows the status of the interrupt, even if FPGA_IRQEN[SW7] is
cleared.
Indicates the SW6_b signal is asserted. This bit shows the status of the interrupt, even if FPGA_IRQEN[SW6] is
cleared.
Indicates the corresponding interrupt PCI_IRQ line is asserted. These bits show the status of interrupt, even if the
corresponding FPGA_IRQEN[PCI] bit is cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
FPGA Interrupt Request Enable Register (FPGA_IRQEN)
FPGA Interrupt Request Status Register (FPGA_IRQSTATUS)
Table 14. FPGA_IRQSTATUS Field Descriptions
Table 13. FPGA_IRQEN Field Descriptions
Figure 13. FPGA_IRQSTATUS Register
Figure 4-12. FPGA_IRQEN Register
M54455EVB User’s Manual, Rev. 4
Description
Description
8
8
7
7
6
6
SW7 SW6
0
0
5
5
0
0
4
4
0 0 0 0
0 0 0 0
3
3
2
2
PCI
PCI
1
1
0
0
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