M54455EVB Freescale, M54455EVB Datasheet - Page 13

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

The following pseudocode illustrates the input clock determination logic:
Refer to
system clock frequencies generated by the CY22393.
There is a provision on the M54455EVB for clocking the MCF5445x with a 25MHz crystal instead of the
33/66MHz external clock. A cut-trace (CT11) can be modified to route the provided 25MHz crystal
oscillator circuit to the EXTAL input. Refer to
Freescale Semiconductor
1
MCF5445x Input Clock
MCF5445x USB Clock
RMII Ethernet Clocks
CLKC is disabled by default. Instead, USBCLKIN is driven by the 60MHz clock output of the ULPI PHY. However, JP918
provides an option to select CLKC as the source for USBCLKIN. If this is selected, the CY22393 must be programmed via
I
2
ULPI PHY Clock
C to generate a 60MHz clock signal.
PCI Clock
1
M66EN signal
Section 4.13,
Clock
if ((H4[3:4] shunt is not installed) and
{
}
else
{
}
Indicates the default values.
—
—
1
0
1
(no 33MHz PCI cards installed (M66EN logic 1)) and
(FPGA_PCICLKCFG[CLKGENS2EN] is set))
S2 = 1; PCI Clocks and MCF5445x input clock are 66MHz
S2 = 0; PCI Clocks and MCF5445x input clock are 33MHz
Table 5. PCI Clocks and MCF5445x Input Clock Speed Selection
“FPGA” for details on the FPGA_PCICLKCFG register.
CY22393
Output
CLKA
CLKB
CLKC
CLKD
CLKE
FPGA_PCICLKCFG
[CLKGENS2EN]
—
0
—
1
S2 Value
1
N/A
N/A
N/A
Table 6. Clock Generator Outputs
0
1
0
1
M54455EVB User’s Manual, Rev. 4
Frequency (MHz)
Default Clock
Disabled
Figure 5
33
66
33
66
24
50
Jumper Shunt OFF
Jumper Shunt ON
H4[3:4] Jumper
1
for details on how to make this modification.
—
—
Clock driven into the EXTAL pin on the MCF5445x.
This is the operating frequency in limp mode and the
PLL reference when the PLL is enabled.
Duplicate of the MCF5445x input clock. This is driven
to clock buffers and on to each PCI slot, the FPGA,
and the CPLD.
MCF5445x USB clock
Reference clock for the external ULPI PHY
Duplicate, matched clocks driven to each MCF5445x
FEC RMII clock input and to the external dual Ethernet
PHY
1
Resulting
S2 Value
0
Description
0
0
1
1
1
Table 6
PCI Bus Speed
CPU input and
33 MHz
33 MHz
33 MHz
66 MHz
shows the default
1
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