AT83C26-RKRUL Atmel, AT83C26-RKRUL Datasheet - Page 5

• Manufacturer Part Number: AT83C26-RKRUL
• Description: RFID Modules & Development Tools 3V Smart card reader
• Manufacturer: Atmel

7511D–SCR–02/07
Table 1. Ports Description (Continued)
Pin number
VQFP48 or
QFN48
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Pad Name
LIA
CVSS1
VCC
VSS
BYPASS
SDA
SCL
IO2
IO1
AUX2
AUX1
A1/RST
A2/CK
CLK
INT
EVCC
Pad Internal
Power Supply
VCC
VCC
VCC
EVCC
EVCC
EVCC
EVCC
EVCC
EVCC
EVCC
VCC
Pad Type
open drain
open drain
open drain
pull up
pull up
pull up
pull up
PWR
PWR
PWR
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
Description
DC/DCA input.
LIA must be tied to VCC pin through an external coil (typically 10µH) and
provides the current for the charge pump of the DC/DCA converter.
It may be directly connected to VCC if the step-up converter is not used
(see STEPREGA bit in SC1_CFG4 register and see minimum VCC
values in Table 50.for class A and Table 51. for class B)
DC/DCA input.
This pin must be directly connected to the VSS of power supply.
VCC is used to power the internal voltage regulators and I/O buffers.
Ground.
A high level on this pin activates a low power consumption mode with
internal regulator bypassed.
Micro controller interface function: TWI serial data.
An external pull up must be connected on SDA pin (4.7kOhms).
Micro controller interface function: TWI clock.
An external pull up must be connected on SCL pin (4.7kOhms).
The behavior of this pin depends on IOSEL[3/0] bits values (see
IO_SELECT register).
The behavior of this pin depends on IOSEL[3/0] bits values (see
IO_SELECT register).
The behavior of this pin depends on IOSEL[3/0] bits values (see
IO_SELECT register).
The behavior of this pin depends on IOSEL[3/0] bits values (see
IO_SELECT register).
The TWI address depends on the value present on this pin at reset.
If CRST transparent mode is selected, the A1/RST signal is connected to
CRST1 or CRST2 pins (see CRST_SEL1 and CRST_SEL2 bits
respectively in SC1_CFG4 and SC2_CFG2 registers).
The TWI address depends on the value present on this pin at reset.
If CCLKn transparent mode is selected, the A2/CK signal is connected to
CCLKn pins (with n=1 to 5).
See CKSn[2:0] bits respectively in SC1_CFG1, SC2_CFG2, SC3_CFG2,
SC4_CFG2, SC5_CFG2 registers.
Master clock.
Interruption status.
An internal pull up to VCC can be activated in the pin if necessary using
INT_PULLUP bit in SC1_CFG4 (deactivated by default).
Extra supply voltage (Micro controller power supply).
EVCC is used to supply the internal level shifters of host interface pins.
EVCC is connected to the host power supply.
EVCC voltage can be directly connected to VCC if the host power supply
and the AT83C26 power supply is the same.
AT83C26
5