MAX7060ATG/V+ Maxim Integrated Products, MAX7060ATG/V+ Datasheet - Page 20

• Manufacturer Part Number: MAX7060ATG/V+
• Description: RF Transmitter 300MHz to 450MHz Fre quency-and-Output-Po
• Manufacturer: Maxim Integrated Products

Specifications of MAX7060ATG/V+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Register Summary
Table 2. Configuration Registers
280MHz to 450MHz Programmable
ASK/FSK Transmitter
The following tables provide information on the MAX7060 registers.
20
Conf2
IOConf0
IOConf1
Tstep
PAstep
PApwr
FHigh0
FHigh1
FCenter0
FCenter1
Ident
Conf0
Conf1
Conf2
IOConf0
IOConf1
Tstep
PAstep
PApwr
FHigh0
FHigh1
FCenter0
FCenter1
FLow0
FLow1
FLoad
EnableReg
DataReg
Status
REGISTER
Ident
Conf0
Conf1
REGISTER
_____________________________________________________________________________________
ADDRESS
0x0C
0x08
0x09
0x0A
0x0B
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0F
0x10
0x11
0x12
ckdiv_2
fce_15
fhi_15
BIT 7
fce_7
fixed
fhi_7
—
—
—
—
—
—
1
Read-only register used for identification purpose. The content of this register is always 0xA6.
Configuration 0 register. Controls the GPO1 boost mode, PLL bandwidth, analog shaping, crys-
tal clock output, and the modulation mode (ASK/FSK).
Configuration 1 register. Controls the clock output frequency divider and the capacitance at the
PA output.
Configuration 2 register. Controls the emulation mode.
IO configuration 0 register. Selects the status register bus for SPI operation.
IO configuration 1 register. Selects the outputs of GPO1 and GPO2_MOD pins.
Digital shaping time step register. Controls the time step in the digital shaping.
Digital shaping power step register. Controls the power step in the digital shaping.
Final power register. Controls the final output power.
High-frequency 0 register (upper byte). Sets the high frequency in FSK transmission.
High-frequency 1 register (lower byte). Sets the high frequency in FSK transmission.
Center-frequency 0 register (upper byte). Sets the carrier frequency in ASK transmission.
Center-frequency 1 register (lower byte). Sets the carrier frequency in ASK transmission.
Low-frequency 0 register (upper byte). Sets the low frequency in FSK transmission.
Low-frequency 1 register (lower byte). Sets the low frequency in FSK transmission.
Frequency-load register. Performs the frequency-load function.
Enable register. Register equivalent of ENABLE pin.
Datain register. Register equivalent of DIN pin.
Status register
ckdiv_1
fxmode
gp2s_2
gp1bst
fce_14
fhi_14
BIT 6
fce_6
fhi_6
—
—
—
—
0
fxpwr_1
ckdiv_0
gp2s_1
fce_13
fhi_13
fce_5
BIT 5
pllbw
fhi_5
—
—
—
—
1
anshp_1
papwr_4
pastp_4
fxpwr_0
gp2s_0
fce_12
cap_4
fhi_12
BIT 4
fce_4
fhi_4
—
—
0
DESCRIPTION
papwr_3
anshp_0
pastp_3
tstep_3
fxhdev
fce_11
DATA
cap_3
fhi_11
BIT 3
fce_3
fhi_3
—
—
0
papwr_2
pastp_2
gp1s_2
tstep_2
tmux_2
fxfrq_2
fce_10
clksby
cap_2
fhi_10
BIT 2
fce_2
fhi_2
1
papwr_1
pastp_1
gp1s_1
tstep_1
tmux_1
fxfrq_1
cap_1
clkout
BIT 1
fce_9
fce_1
fhi_9
fhi_1
Register Details
1
papwr_0
pastp_0
gp1s_0
tmux_0
tstep_0
fxfrq_0
cap_0
mode
BIT 0
fce_8
fce_0
fhi_8
fhi_0
0
MODE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R