MAX7060ATG/V+ Maxim Integrated Products, MAX7060ATG/V+ Datasheet - Page 15

• Manufacturer Part Number: MAX7060ATG/V+
• Description: RF Transmitter 300MHz to 450MHz Fre quency-and-Output-Po
• Manufacturer: Maxim Integrated Products

Specifications of MAX7060ATG/V+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency pull-
ing is given by:
where:
When the crystal is loaded as specified (i.e., C
C
The MAX7060 has two GPO pins in SPI mode (GPO2_
MOD and GPO1) and one GPO in manual mode (GPO1).
The GPO1 pin can serve as a clock for a microprocessor
or any other GPO function in SPI mode. In manual mode,
this pin outputs the synthesizer lock-detect (lockdet)
status, after which the user can send data through the
DIN pin.
Figure 2. SPI Format
SPEC
f
f
C
C
C
C
SCLK_PWR0
P
GPO2_MOD
P
SDI_PWR1
M
CASE
SPEC
LOAD
=
is the amount the crystal frequency pulled in ppm
CS_DEV
), the frequency pulling equals zero.
C
is the motional capacitance of the crystal
2
M
is the specified load capacitance
is the case capacitance



is the actual load capacitance
C
CASE
______________________________________________________________________________________
+
1
C
LOAD
DO7
DI7
General-Purpose Output
DO6
−
DI6
(GPO)/Clock Outputs
C
CASE
280MHz to 450MHz Programmable
DO5
DI5
DO4
DI4
1
+
DATA 1
C
SPEC
DO3
DI3
DO2



DI2
LOAD
×
10
DO1
DI1
6
=
DO0
DI0
The GPO2_MOD pin acts as the SPI data output when
the CS_DEV pin is low, in SPI mode. When CS_DEV is
high, it acts as a GPO that can output various internal
signals, such as the synthesizer lock detect (lockdet).
In SPI mode, the output clock that can be routed through
GPO1 is a divided version of the crystal frequency. The
divide ratio is set through the MAX7060 registers, and
the divide settings are 1 (no division), 2, 4, 8, or 16. An
external buffer is recommended to drive external devices
if divide settings of 1, 2, and 4 are selected.
The MAX7060 utilizes a 4-wire SPI protocol for pro-
gramming its registers, configuring and controlling the
operation of the whole transmitter. For SPI operation, the
FREQ2, FREQ1, and FREQ0 pins must be reset to 0.
The following digital I/Os control the operation of the SPI:
Figure 2 shows the general timing diagram of the SPI
protocol.
Any number of 8-bit data bursts (Data 1, Data 2 … Data
n) can be sent within one cycle of the CS_DEV pin, to
allow for burst-write or burst-read operations. The SPI
data output signal is routed through the GPO2_MOD pin
when CS_DEV is low.
CS_DEV
SDI_PWR1
SCLK_PWR0
GPO2_MOD
ASK/FSK Transmitter
DO7
DI7
DO6
DI6
DO5
Serial Peripheral Interface (SPI)
DI5
Active-low SPI chip select
SPI data Input
SPI clock
SPI data output
DO4
DI4
DATA n
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
15