4308-52 Peregrine Semiconductor, 4308-52 Datasheet - Page 8
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4308-52
Manufacturer Part Number
4308-52
Description
IC DSA 5BIT 50 OHM 20-QFN
Manufacturer
Peregrine Semiconductor
Series
UltraCMOS™r
Datasheet
1.4308-52.pdf
(11 pages)
Specifications of 4308-52
Attenuation Value
31dB
Tolerance
±0.2dB
Frequency Range
0 ~ 4GHz
Impedance
50 Ohm
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
1046-1035-2
Figure 17. Serial Interface Timing Diagram
Figure 18. Parallel Interface Timing Diagram
Table 8. Serial Interface AC Characteristics
V
Note:
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 11
DD
Symbol
Parallel Data
Clock
Data
LE
= 3.0 V, -40° C < T
f
t
t
t
t
t
t
C16:C1
Clk
ClkH
ClkL
LESUP
LEPW
SDSUP
SDHLD
f
programming sections of the functional pattern are clocked
at 10 MHz to verify f
Clk
is verified during the functional pattern test. Serial
MSB
LE
Serial data clock
frequency (Note 1)
Serial clock HIGH time
Serial clock LOW time
LE set-up time after last
clock falling edge
LE minimum pulse width
Serial data set-up time
before clock rising edge
Serial data hold time
after clock falling edge
t
SDSUP
Parameter
t
t
SDHLD
A
PDSUP
< 85° C, unless otherwise specified
clk
specification.
t
LEPW
Min
30
30
10
30
10
10
Max
10
t
PDHLD
LSB
t
LESUP
Unit
MHz
ns
ns
ns
ns
ns
ns
t
LEPW
MSB (first in)
Table 7. 5-Bit Attenuator Serial Programming
Register Map
Note: The stop bit (B0) must always be low to prevent the attenuator
Table 9. Parallel Interface AC Characteristics
V
C16
B5
DD
Symbol
↑
= 3.0 V, -40° C < T
t
t
t
LEPW
PDSUP
PDHLD
Document No. 70-0162-04 │ UltraCMOS™ RFIC Solutions
from entering an unknown state.
B4
C8
LE minimum pulse width
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
Parameter
B3
C4
A
< 85° C, unless otherwise specified
B2
C2
Min
10
10
10
Product Specification
B1
C1
Max
LSB (last in)
PE4308
B0
↑
0
Unit
ns
ns
ns