STLC2411 STMicroelectronics, STLC2411 Datasheet - Page 20

• Manufacturer Part Number: STLC2411
• Description: Bluetooth Class I 1.8V 0.721Mbps 132-Pin TFBGA
• Manufacturer: STMicroelectronics

Specifications of STLC2411

• Package: 132TFBGA
• Power Class: Class I
• Maximum Data Rate: 0.721 Mbps
• Operating Supply Voltage: 1.8 V
• Lead Free Status / Rohs Status: Not Compliant

STLC2411
interface is programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
Directions of PCM_A and PCM_B are software configurable.
Three additional PCM_SYNC signals can be provided via the GPIOs. See section 12 for more details.
Figure 9. PCM (A-law, -law) standard mode
Figure 10. Linear mode
Table 13. PCM interface timing.
20/25
PCM Interface
PCM_SYNC
PCM_SYNC
PCM_CLK
F
PCM_CLK
Symbol
PCM_A
PCM_B
PCM_A
PCM_B
F
– PCM_CLK :
– PCM_SYNC :
– PCM_A :
– PCM_B :
pcm_sync
pcm_clk
t
t
t
t
t
t
t
WCH
WCL
WSH
SSC
SDC
HCD
DCD
Frequency of PCM_CLK (master)
Frequency of PCM_SYNC
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
Setup time, PCM_SYNC high to PCM_CLK low
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input invalid
Delay time, PCM_CLK high to PCM_A/B output valid
0
0
1
1
PCM clock
PCM 8kHz sync
PCM data
PCM data
2
2
3
3
B
B
4
4
Description
5
5
6
6
7
7
8
8
125 s
125 s
9
9
10
10
11
11
12
12
13
13
14
14
Min
200
200
200
100
100
100
15
15
2048
Typ
8
Max
150
D02TL558
D02TL559
Unit
kHz
kHz
B
B
ns
ns
ns
ns
ns
ns
ns