LFE2M50E-7FN672C LATTICE SEMICONDUCTOR, LFE2M50E-7FN672C Datasheet - Page 100
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LFE2M50E-7FN672C
Manufacturer Part Number
LFE2M50E-7FN672C
Description
FPGA LatticeECP2M Family 48000 Cells 90nm (CMOS) Technology 1.2V 672-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M50E-7FN672C
Package
672FBGA
Family Name
LatticeECP2M
Device Logic Units
48000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
4246528
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50E-7FN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE2M50E-7FN672C
Manufacturer:
LATTICE
Quantity:
20 000
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Figure 3-15. sysCONFIG Parallel Port Write Cycle
Figure 3-16. sysCONFIG Slave Serial Port Timing
Figure 3-17. Power-On-Reset (POR) Timing
CCLK (input)
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
V
1. Time taken from V
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
CCLK
CS1N
BUSY
D[0:7]
CC
CSN
DOUT
/V
CFG[2:0]
DIN
CCAUX
DONE
CCLK
INITN
1
1
2
3
CC
or V
t
SUCBDI
CCAUX
, whichever is the last to reach its V
t
t
SUWD
SUCS
Byte 0
t
SUSCDI
t
ICFG
t
SUCFG
t
BSCL
3-48
Byte 1
t
SSCL
t
HCBDI
t
VMC
Valid
Byte 2
MIN
t
DCB
DC and Switching Characteristics
.
LatticeECP2/M Family Data Sheet
t
t
HCFG
BSCYC
t
t
BSCH
CODO
t
SSCH
Byte n
t
HSCDI
t
HCS
t
HWD
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