XC6VCX75T-2FF484C Xilinx Inc, XC6VCX75T-2FF484C Datasheet - Page 46

• Manufacturer Part Number: XC6VCX75T-2FF484C
• Description: FPGA Virtex®-6 CXT Family 74496 Cells 40nm (CMOS) Technology 1V 484-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC6VCX75T-2FF484C

• Package: 484FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 74496
• Number Of Registers: 93120
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 240
• Ram Bits: 5750784

Table 57: MMCM Specification (Cont’d)
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
T
T
T
T
F
F
T
RST
F
F
T
T
T
T
T
T
STATPHAOFFSET
OUTJITTER
OUTDUTY
LOCKMAX
OUTMAX
OUTMIN
EXTFDVAR
PFDMAX
PFDMIN
FBDELAY
MMCMDCK_PSEN
MMCMCKD_PSEN
MMCMDCK_PSINCDEC
MMCMCKD_PSINCDEC
MMCMCKO_PSDONE
When DIVCLK_DIVIDE = 3 or 4, F
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
Calculated as F
When CASCADE4_OUT = TRUE, F
In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.
MINPULSE
Symbol
/
VCO
/
/128 assuming output duty cycle is 50%.
Static Phase Offset of the MMCM Outputs
MMCM Output Jitter
MMCM Output Clock Duty Cycle Precision
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to High or Optimized
Maximum Frequency at the Phase Frequency Detector
with Bandwidth Set to Low
Minimum Frequency at the Phase Frequency Detector
with Bandwidth Set to High or Optimized
Minimum Frequency at the Phase Frequency Detector
with Bandwidth Set to Low
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
Setup and Hold of Phase Shift Increment/Decrement
Phase Shift Clock-to-Out of PSDONE
INMAX
OUTMIN
is 315 MHz.
is 0.036 MHz.
(4)
Description
www.xilinx.com
(6)(7)
(8)
(3)
(5)
< 20% of clock input period or 1 ns
3 ns Max or one CLKIN cycle
1.04/0.00
1.04/0.00
10.00
0.12
0.20
4.69
0.38
700
100
450
300
135
1.5
-2
Speed Grade
Virtex-6 CXT Family Data Sheet
Max
Note 1
1.04/0.00
1.04/0.00
10.00
0.12
0.20
4.69
0.38
100
700
450
300
135
1.5
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
µs
ns
ns
ns
ns
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