XC6VCX240T-1FFG1156C Xilinx Inc, XC6VCX240T-1FFG1156C Datasheet - Page 42

• Manufacturer Part Number: XC6VCX240T-1FFG1156C
• Description: FPGA Virtex®-6 CXT Family 241152 Cells 40nm (CMOS) Technology 1V 1156-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX240T-1FFG1156C

• Package: 1156FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 241152
• Number Of Registers: 301440
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 600
• Ram Bits: 15335424
• Number Of Logic Elements/cells: 241152
• Number Of Labs/clbs: 18840
• Total Ram Bits: 15335424
• Number Of I /o: 600
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configuration Switching Characteristics
Table 52: Configuration Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Power-up Timing Characteristics
T
T
T
T
Master/Slave Serial Mode Programming Switching
T
T
T
F
F
F
SelectMAP Mode Programming Switching
T
T
T
T
T
T
F
F
F
Boundary-Scan Port Timing Specifications
T
T
F
F
F
PL
POR
ICCK
PROGRAM
DCCK
DSCCK
CCO
MCCK
MCCKTOL
MSCCK
SMDCCK
SMCSCCK
SMCCKW
SMCKCSO
SMCO
SMCKBY
SMCCK
RBCCK
MCCKTOL
TAPTCK
TCKTDO
TCK
TCKB_MIN
TCKB
(1)
(1)
/T
/T
/T
CCKD
/T
/T
SCCKD
/T
TCKTAP
SMCCKD
SMWCCK
SMCCKCS
Symbol
Program Latency
Power-on-Reset
CCLK (output) delay
Program Pulse Width
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT at 2.5V
DOUT at 1.8V
Maximum CCLK frequency, serial modes
Frequency Tolerance, master mode with respect to
nominal CCLK
Slave mode external CCLK
SelectMAP Data Setup/Hold
CSI_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
(330  pull-up resistor required)
CCLK to DATA out in readback at 2.5V
CCLK to DATA out in readback at 1.8V
CCLK to BUSY out in readback at 2.5V
CCLK to BUSY out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK
Maximum Readback Frequency with respect to nominal
CCLK
Frequency Tolerance with respect to nominal CCLK
TMS and TDI Setup time before TCK/ Hold time after
TCK
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
Minimum boundary-scan TCK clock frequency when
using IEEE Std 1149.6 (AC-JTAG). Minimum operating
temperature for IEEE Std 1149.6 is 0°C.
Maximum boundary-scan TCK clock frequency
(1)
www.xilinx.com
Description
10.0/0.0
Virtex-6 CXT Family Data Sheet
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
3.0/2.0
15/55
400
250
100
100
100
100
Speed Grade
55
55
66
15
66
-2
3
6
6
7
8
8
6
6
6
6
10.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
4.0/0.0
3.0/2.0
15/55
400
250
100
100
100
100
55
55
66
15
66
-1
3
6
6
7
8
8
6
6
6
6
ms, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Min
ms, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
%
%
42