XC6VCX240T-1FFG1156C Xilinx Inc, XC6VCX240T-1FFG1156C Datasheet - Page 30

• Manufacturer Part Number: XC6VCX240T-1FFG1156C
• Description: FPGA Virtex®-6 CXT Family 241152 Cells 40nm (CMOS) Technology 1V 1156-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX240T-1FFG1156C

• Package: 1156FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 241152
• Number Of Registers: 301440
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 600
• Ram Bits: 15335424
• Number Of Logic Elements/cells: 241152
• Number Of Labs/clbs: 18840
• Total Ram Bits: 15335424
• Number Of I /o: 600
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1156-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in
X-Ref Target - Figure 14
Table 41: Output Delay Measurement Methodology
DS153 (v1.6) February 11, 2011
Product Specification
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
FPGA Output
Figure 14: Single Ended Test Setup
Description
V
REF
R
C
(probe capacitance)
REF
REF
Figure 14
V
(voltage level when taking
delay measurement)
MEAS
ds152_06_042109
and
Figure
www.xilinx.com
15.
HSTL_III_18
SSTL18_I
LVDS_25
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I
HSTL_II
HSTL_III
HSTL_I_18
HSTL_II_18
SSTL18_II
SSTL2_I
SSTL2_II
LVDS_25
BLVDS_25
X-Ref Target - Figure 15
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
2. Record the time to V
3. Simulate the output driver of choice into the actual PCB
4. Record the time to V
5. Compare the results of steps 2 and 4. The increase or
I/O Standard
Attribute
test setup, using values from
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
decrease in delay yields the actual propagation delay of
the PCB trace.
FPGA Output
Figure 15: Differential Test Setup
REF
, R
REF
, C
C
MEAS
MEAS
Virtex-6 CXT Family Data Sheet
R
REF
REF
100
100
100
()
1M
1M
1M
1M
50
25
50
50
25
50
50
25
50
25
REF
.
.
, and V
Table
C
(pF)
REF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MEAS
(1)
41.
R
fully describe
REF
V
V
V
V
V
V
V
V
V
ds152_07_042109
1.25
0.75
0.75
MEAS
(V)
0
0
0
1.1
0.9
0.9
REF
REF
REF
REF
REF
REF
REF
REF
(2)
(2)
(2)
V
MEAS
+
–
V
0.75
0.75
1.25
1.25
(V)
1.5
0.9
0.9
1.8
0.9
0.9
1.2
1.2
REF
0
0
0
0
0
30