XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 340

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-17
340
1 Clock Region
IDELAYCTRL
IDELAYCTRL Usage and Design Guidelines
This section describes using the IDELAYCTRL modules, design guidelines, and
recommended usage in Virtex-5 devices.
Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools auto-
replicate IDELAYCTRL instances throughout the entire device. When IDELAYCTRL
instances are replicated to clock regions but not used, the extra instances are trimmed out
of the design automatically by the ISE software. The signals connected to the RST and
REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the
corresponding input ports of the replicated IDELAYCTRL instances.
There are two special cases:
1.
Figure 7-17: Relative Locations of IDELAYCTRL Modules
When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided in
the Libraries Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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