XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 138

• Manufacturer Part Number: XC5VSX50T-1FFG665I
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Block RAM
138
Block RAM Timing Model
Figure 4-15
This example takes the simplest paths on and off chip (these paths can vary greatly
depending on the design). This timing model demonstrates how and where the block
RAM timing parameters are used.
•
•
•
•
X-Ref Target - Figure 4-15
Synchronous
Write Enable
Set/Reset
NET = Varying interconnect delays
T
T
T
Address
IOPI
IOOP
BCCKO_O
Enable
Clock
Data
= Pad to I-output of IOB delay
= O-input of IOB to pad delay
illustrates the delay paths associated with the implementation of block RAM.
= BUFGCTRL delay
[T
[T
[T
[T
[T
[T
IOPI
IOPI
IOPI
IOPI
IOPI
IOPI
+ NET] + T
+ NET]
Figure 4-15: Block RAM Timing Model
+ NET] + T
+ NET] + T
[T
+ NET] + T
+ NET] + T
www.xilinx.com
BCCKO_O
BUFGCTRL
RCCK_ADDR
RCCK_WEN
RCCK_SSR
RCCK_EN
RDCK_DI
+ NET]
DI
ADDR
WE
EN
SSR
Block RAM
CLK
FPGA
DO
T
RCKO_DO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
+ [NET + T
IOOP
ug190_4_14_022207
]
Data