XC5VLX85T-1FF1136C Xilinx Inc, XC5VLX85T-1FF1136C Datasheet - Page 324

• Manufacturer Part Number: XC5VLX85T-1FF1136C
• Description: FPGA Virtex®-5 Family 82944 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX85T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 82944
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 3981312
• Number Of Logic Elements/cells: 82944
• Number Of Labs/clbs: 6480
• Total Ram Bits: 3981312
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 7: SelectIO Logic Resources
324
Table 7-5: ILOGIC Switching Characteristics
Note:
parameters.
Setup/Hold
T
T
T
Combinatorial
T
Sequential Delays
T
T
T
T
ICE1CK
ISRCK
IDOCK
IDI
IDLO
ICKQ
ICE1Q
RQ
Symbol
The DDLY timing diagrams and parameters are identical to the D timing diagrams and
/T
/T
/T
ICKSR
IOCKD
ICKCE1
CE1 pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK
D pin to O pin propagation delay, no Delay
D pin to Q1 pin using flip-flop as a latch without Delay
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
www.xilinx.com
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010