XC3SD3400A-4CSG484I Xilinx Inc, XC3SD3400A-4CSG484I Datasheet - Page 43

• Manufacturer Part Number: XC3SD3400A-4CSG484I
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA, CSPBGA
• No. Of Logic Blocks: 5968
• No. Of Gates: 3400000
• No. Of Macrocells: 53712
• Family Type: Spartan-3A
• No. Of Speed Grades: 4
• No. Of I/o's: 309
• Clock Management: DCM
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 35: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
Clock to Out from Output Register Clock to Output Pin
T
Clock to Out from Pipeline Register Clock to Output Pins
T
Clock to Out from Input Register Clock to Output Pins
T
T
T
T
Combinatorial Delays from Input Pins to Output Pins
T
T
T
T
T
T
Maximum Frequency
F
DSPCKO_PP
DSPCKO_PM
DSPCKO_PA
DSPCKO_PB
DSPCKO_PC
DSPCKO_PD
DSPDO_AP
DSPDO_BP
DSPDO_BP
DSPDO_CP
DSPDO_DP
DSPDO_OPP
MAX
Symbol
To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.
"Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not
applicable.
The numbers in this table are based on the operating conditions set forth in
CLK (PREG) to P output
CLK (MREG) to P output
CLK (AREG) to P output
CLK (BREG) to P output
CLK (CREG) to P output
CLK (DREG) to P output
A or B input to P output
B input to P output
C input to P output
D input to P output
OPMODE input to P output
All registers used
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Pre-adder
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
–
–
–
–
–
–
–
–
Multiplier Post-adder
Table
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
–
–
–
7.
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
–
Max
1.26
3.16
1.94
6.33
7.45
3.37
7.33
2.78
4.60
5.65
3.49
5.79
6.74
2.76
6.81
7.12
287
Speed Grade
-5
Max
1.44
3.63
2.23
7.27
8.56
3.87
8.42
3.19
5.28
6.49
4.01
6.65
7.74
3.17
7.82
8.18
250
-4
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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