XC3S1600E-5FG400C Xilinx Inc, XC3S1600E-5FG400C Datasheet - Page 230

• Manufacturer Part Number: XC3S1600E-5FG400C
• Description: FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S1600E-5FG400C

• Package: 400FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 33192
• Device Logic Units: 3688
• Device System Gates: 1600000
• Number Of Registers: 29504
• Maximum Internal Frequency: 657 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 663552

Pinout Descriptions
Table 154: FG484 Package Pinout (Continued)
User I/Os by Bank
Table 155
distributed between the four I/O banks on the FG484 pack-
age.
Table 155: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
230
Notes:
1.
2.
VCCAUX VCCAUX
Top
Right
Bottom
Left
TOTAL
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
indicates how the 304 available user-I/O pins are
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
I/O Bank
XC3S1600E
Pin Name
0
1
2
3
Maximum
376
I/O
94
94
94
94
FG484
W11
Ball
K11
K13
J10
L10
L11
L12
L14
M9
K9
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Type
214
I/O
56
50
45
63
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Table 154: FG484 Package Pinout (Continued)
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
INPUT
Bank
22
16
18
16
72
All Possible I/O Pins by Type
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
DUAL
XC3S1600E
Pin Name
21
24
46
1
0
DS312-4 (v3.8) August 26, 2009
VREF
28
7
7
7
7
(1)
Product Specification
FG484
M11
M12
M13
Ball
N10
N12
N14
P13
CLK
0
0
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
16
8
8
(2)
(2)
Type
(1)
R