XC3S1200E-4FG400I Xilinx Inc, XC3S1200E-4FG400I Datasheet - Page 4
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XC3S1200E-4FG400I
Manufacturer Part Number
XC3S1200E-4FG400I
Description
FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FG400I
Package
400FBGA
Family Name
Spartan®-3E
Device Logic Cells
19512
Device Logic Units
2168
Device System Gates
1200000
Number Of Registers
17344
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
516096
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
304
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Architectural Overview
The Spartan-3E family architecture consists of five funda-
mental programmable functional elements:
•
•
•
•
4
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Notes:
1.
The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1: Spartan-3E Family Architecture
www.xilinx.com
•
These elements are organized as shown in
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting sig-
nals among them. Each functional element has an associ-
ated switch matrix that permits multiple connections to the
routing.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
DS312-1 (v3.8) August 26, 2009
Product Specification
Figure
1. A ring
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