XC3S1200E-4FG400I Xilinx Inc, XC3S1200E-4FG400I Datasheet - Page 157
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XC3S1200E-4FG400I
Manufacturer Part Number
XC3S1200E-4FG400I
Description
FPGA Spartan®-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FG400I
Package
400FBGA
Family Name
Spartan®-3E
Device Logic Cells
19512
Device Logic Units
2168
Device System Gates
1200000
Number Of Registers
17344
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
516096
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
304
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 119: Configuration Timing Requirements for Attached SPI Serial Flash
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
Symbol
CCS
DSU
DH
V
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Description
www.xilinx.com
T
T
T
CCS
V
f
DSU
DC and Switching Characteristics
C
T
≤
≥
DH
T
Requirement
≤
≤
------------------------------ -
T
MCCLn
T
≤
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
–
(
T
–
–
DCC
T
)
T
CCO
CCO
Units
MHz
ns
ns
ns
ns
157
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