XC3S100E-4VQG100I Xilinx Inc, XC3S100E-4VQG100I Datasheet - Page 43

• Manufacturer Part Number: XC3S100E-4VQG100I
• Description: FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4VQG100I

• Package: 100VTQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 2160
• Device Logic Units: 240
• Device System Gates: 100000
• Number Of Registers: 1920
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 66
• Ram Bits: 73728
• Number Of Logic Elements/cells: 2160
• Number Of Labs/clbs: 240
• Total Ram Bits: 73728
• Number Of I /o: 66
• Number Of Gates: 100000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Setting the WRITE_MODE attribute to a value of
NO_CHANGE, puts the DO outputs in a latched state when
asserting WE. Under this condition, the DO outputs retain
DS312-2 (v3.8) August 26, 2009
Product Specification
R
Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
ADDR
Data_in
CLK
WE
DO
EN
DI
DISABLED
0000
DI
Internal
Memory
XXXX
aa
READ
MEM(aa)
www.xilinx.com
DO
bb
MEM(bb)=1111
1111
WRITE
the data driven just before WE is asserted. NO_CHANGE
timing is shown in the portion of
is High.
No change during write
2222
cc
MEM(cc)=2222
WRITE
dd
DS312-2_07_020905
XXXX
READ
MEM(dd)
Figure 35
Functional Description
during which WE
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