XC3S100E-4VQG100I Xilinx Inc, XC3S100E-4VQG100I Datasheet - Page 111

• Manufacturer Part Number: XC3S100E-4VQG100I
• Description: FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S100E-4VQG100I

• Package: 100VTQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 2160
• Device Logic Units: 240
• Device System Gates: 100000
• Number Of Registers: 1920
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 66
• Ram Bits: 73728
• Number Of Logic Elements/cells: 2160
• Number Of Labs/clbs: 240
• Total Ram Bits: 73728
• Number Of I /o: 66
• Number Of Gates: 100000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Powering Spartan-3E FPGAs
For additional information, refer to the “Powering Spartan-3
Generation FPGAs” chapter in UG331.
Table 70: Spartan-3E Voltage Supplies
In a 3.3V-only application, all four V
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the V
banks. Refer to
can be intermixed within a single I/O bank.
DS312-2 (v3.8) August 26, 2009
Product Specification
CRC
Persist
Option Name
VCCO_0
VCCO_1
VCCO_2
VCCO_3
V
Supply
V
Input
CCAUX
CCINT
R
Internal core supply voltage. Supplies all internal logic functions, such as CLBs,
block RAM, and multipliers. Input to Power-On Reset (POR) circuit.
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential
drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset
(POR) circuit.
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In
connects to the same voltage as the Flash PROM.
Supplies the output buffers in I/O Bank 2, the bank along the bottom edge of the
FPGA. Connects to the same voltage as the FPGA configuration source. Input
to Power-On Reset (POR) circuit.
Supplies the output buffers in I/O Bank 3, the bank along the left edge of the
FPGA.
I/O Banking Rules
Pins/Function
interface pins,
Configuration
Configuration
Slave mode,
SelectMAP
BPI mode,
Affected
Byte-Wide Peripheral Interface (BPI) Parallel Flash
(default)
Enable
Disable
Values
CCO
for which I/O standards
Yes
CCO
No
supplies connect to
inputs of different
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Turn off CRC checking.
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see
configuration and are not available as user-I/O.
Description
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Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in
supply inputs for internal logic functions, V
V
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the V
bank must be connected and must connect to the same
voltage.
Each I/O bank also has an separate, optional input voltage
reference supply, called V
standard that requires a voltage reference such as HSTL or
SSTL, then all V
nected to the same voltage.
CCAUX
. Each of the four I/O banks has a separate V
Description
Mode,
REF
pins within the I/O bank must be con-
Slave Parallel
REF
CCO
. If the I/O bank includes an I/O
connections to a specific I/O
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Selectable, 3.3V, 2.5V,
Functional Description
Mode) are reserved after
Table
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
1.8, 1.5V, or 1.2V
Nominal Supply
70. There are two
Voltage
1.2V
2.5V
CCINT
CCO
and
111