XC3S1000-4FGG456C Xilinx Inc, XC3S1000-4FGG456C Datasheet - Page 19
![FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA](/photos/28/18/281856/xc3s1000-4fgg456c_back__sml.jpg)
XC3S1000-4FGG456C
Manufacturer Part Number
XC3S1000-4FGG456C
Description
FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S1000-4FGG456C
Package
456FBGA
Family Name
Spartan®-3
Device Logic Units
17280
Device System Gates
1000000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
333
Ram Bits
442368
Number Of Logic Elements/cells
17280
Number Of Labs/clbs
1920
Total Ram Bits
442368
Number Of I /o
333
Number Of Gates
1000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1502 - KIT STARTER SPARTAN-3 PCI-E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1333
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1000-4FGG456C
Manufacturer:
XILINX
Quantity:
319
Company:
Part Number:
XC3S1000-4FGG456C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1000-4FGG456C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 10: DCI Terminations
DS099-2 (v2.5) December 4, 2009
Product Specification
Notes:
1.
2.
3.
Controlled impedance output driver
Controlled output driver with half impedance
Single resistor
Split resistors
Split resistors with output driver impedance
fixed to 25Ω
The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of R
for the DV2 standards and R
For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
R
Termination
REF
for all other DCI standards.
IOB
IOB
IOB
IOB
IOB
www.xilinx.com
25Ω
R/2
Schematic
R
V
V
V
CCO
CCO
CCO
Spartan-3 FPGA Family: Functional Description
(1)
R
2R
2R
2R
2R
Z
Z
Z
0
Z
0
Z
0
0
0
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
GTL_DCI
GTLP_DCI
HSTL_III_DCI
HSTL_III_DCI_18
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
SSTL18_I_DCI
SSTL2_I_DCI
SSTL2_II_DCI
Signal Standards
(IOSTANDARD)
(2)
(3)
(2)
(3)
(2)
(2)
REF
19