XC2VP7-5FG456I Xilinx Inc, XC2VP7-5FG456I Datasheet - Page 91
![no-image](/images/no-image-200.jpg)
XC2VP7-5FG456I
Manufacturer Part Number
XC2VP7-5FG456I
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 456-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP7-5FG456I
Package
456FBGA
Family Name
Virtex-II ProÂ
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
248
Ram Bits
811008
Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
248
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2VP7-5FG456I
Manufacturer:
RFMD
Quantity:
1 560
Company:
Part Number:
XC2VP7-5FG456I
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC2VP7-5FG456I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Table 30: RocketIO RXUSRCLK2 Switching Characteristics (Continued)
Table 31: RocketIO TXUSRCLK2 Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Clock
Setup and Hold Relative to Clock
(TXUSRCLK2)
Clock to Out
Clock
RXUSRCLK2 minimum pulse width, High
RXUSRCLK2 minimum pulse width, Low
CONFIGENABLE control input
TXBYPASS8B10B control inputs
TXFORCECRCERR control input
TXPOLARITY control input
TXINHIBIT control inputs
LOOPBACK control inputs
TXRESET control input
TXCHARISK control inputs
TXCHARDISPMODE control inputs
TXCHARDISPVAL control inputs
CONFIGIN data input
TXDATA data inputs
TXBUFERR status output
TXKERR status outputs
TXRUNDISP status outputs
CONFIGOUT data output
TXUSRCLK2 minimum pulse width, High
TXUSRCLK2 minimum pulse width, Low
R
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
T
GCCK
T
GCCK
T
T
T
T
T
GDCK
T
T
GCCK
GCCK
GCCK
GCCK
GCCK
GCCK
T
GDCK
GCCK
GCCK
_CFGEN/T
T
_TCRCE/T
www.xilinx.com
_CFGIN/T
T
T
_TCDM/T
GCKDO
_TKCH/T
T
_TCDV/T
_TBYP/T
_TPOL/T
_TRST/T
_TDAT/T
_TINH/T
GCKST
GCKST
GCKST
T
T
T
T
_LBK/T
GPWH
GPWL
GPWH
GPWL
Symbol
Symbol
_CFGOUT
_TBERR
_TKERR
_TRDIS
_RX2
_RX2
_TX2
_TX2
GCKC
GCKC
GCKC
GCKC
GCKC
GCKC
GCKC
GCKC
GCKC
GCKC
GCKD
GCKD
_CFGEN
_TBYP
_TCRCE
_TPOL
_TINH
_LBK
_TRST
_TKCH
_TCDM
_TCDV
_CFGIN
_TDAT
0.39/ 0.12
0.02/ 0.00
0.02/ 0.00
0.02/ 0.10
0.02/ 0.00
0.02/ 0.00
0.35/ 0.10
0.02/ 0.00
0.35/ 0.10
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
0.54
0.41
1.42
1.42
0.41
0.25
1.42
1.42
-7
-7
Speed Grade
Speed Grade
0.35/ 0.10
0.02/ 0.00
0.44/ 0.14
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
0.02/ 0.10
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
0.35/ 0.10
0.02/ 0.00
1.42
1.42
0.54
0.41
0.41
0.25
1.42
1.42
-6
-6
0.39/ 0.11
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
0.39/ 0.11
0.49/ 0.15
0.02/ 0.00
0.02/ 0.00
0.02/ 0.11
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
2.25
2.25
0.60
0.46
0.46
0.28
2.25
2.25
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
20
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