XC2S300E-6PQG208C Xilinx Inc, XC2S300E-6PQG208C Datasheet - Page 40
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XC2S300E-6PQG208C
Manufacturer Part Number
XC2S300E-6PQG208C
Description
FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S300E-6PQG208C
Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
6912
Device Logic Units
1536
Device System Gates
300000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
65536
Number Of Logic Elements/cells
6912
Number Of Labs/clbs
1536
Total Ram Bits
65536
Number Of I /o
146
Number Of Gates
300000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1326
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Part Number:
XC2S300E-6PQG208C
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Quantity:
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Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
40
Notes:
1.
Output Delay Adjustments (Adj)
T
T
T
T
T
T
T
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables
T
T
T
T
T
T
T
T
T
T
T
T
T
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
OLVCMOS18
T
T
T
T
OLVTTL_F12
OLVTTL_F16
OLVTTL_F24
T
T
OLVTTL_S2
OLVTTL_S4
OLVTTL_S6
OLVTTL_S8
OLVTTL_F2
OLVTTL_F4
OLVTTL_F6
OLVTTL_F8
OLVCMOS2
Symbol
OSSTL3_II
T
OHSTL_IV
OSSLT2_II
T
OPCI33_3
OPCI66_3
OHSTL_III
OSSTL2_I
OSSTL3_I
OLVPECL
T
T
OHSTL_I
T
OGTLP
OLVDS
OGTL
OCTT
OAGP
Constants for Calculating TIOOP
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, C
SL
)
Description
and
Delay Measurement Methodology, page
www.xilinx.com
LVTTL, Slow, 2 mA
LVTTL, Fast, 2 mA
LVCMOS2
LVCMOS18
LVDS
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
AGP
Standard
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
41.
–0.05
–0.20
–0.41
–0.41
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
14.7
13.1
0.09
–1.2
0.49
7.5
4.8
3.0
1.9
1.7
1.3
5.3
3.1
1.0
0.7
2.3
0.8
-7
0
Speed Grade
DS077-3 (v2.3) June 18, 2008
–0.05
–0.20
–0.41
–0.41
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
14.7
13.1
0.09
–1.2
0.49
7.5
4.8
3.0
1.9
1.7
1.3
5.3
3.1
1.0
0.7
2.3
0.8
Product Specification
-6
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R