XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 9

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

DS077-2 (v2.3) June 18, 2008
Architectural Description
Spartan-IIE FPGA Array
The Spartan
Figure
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DS077-2 (v2.3) June 18, 2008
Product Specification
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
3, is composed of five major configurable elements:
®
-IIE user-programmable gate array, shown in
I/O LOGIC
R
DLL
DLL
Figure 3: Basic Spartan-IIE Family FPGA Block Diagram
CLBs
CLBs
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Spartan-IIE FPGA Family:
Functional Description
Product Specification
As can be seen in
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Values stored in static memory cells control all the config-
urable logic elements and interconnect resources. These
values load into the memory cells on power-up, and can
reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
CLBs
CLBs
Figure
DLL
DLL
3, the CLBs form the central logic
DS077_01_052102
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