XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 33

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Power-On Requirements
Spartan
I
power-on. If more current is available, the FPGA can con-
sume more than I
affect reliability.
DC Input and Output Levels
Values for V
Values for V
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
DS077-3 (v2.3) June 18, 2008
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
CCPO
Symbol
Input/Output
LVTTL
LVCMOS2
LVCMOS18
PCI, 3.3V
GTL
GTL+
T
I
I
CCPO
HSPO
CCPO
Standard
The I
Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with V
The ramp time is measured from GND to 1.8V on a fully loaded board.
V
I/Os are not guaranteed to be disabled until V
For more information on designing to meet the power-on specifications, refer to the application note
Requirements for the Spartan-II and Spartan-IIE
CCINT
be provided to the V
(1)
®
CCPO
-IIE FPGAs require that a minimum supply current
Total V
required during power-on
V
AC current per pin during power-on in
hot-swap applications when
V
must not dip in the negative direction during power on.
R
CCINT
IN
IL
OL
> V
requirement applies for a brief time (commonly only a few milliseconds) when V
and V
and V
CCINT
(3,4)
CCO
CCPO
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
CCINT
ramp time
+ 0.4V; duration < 10ns
IH
supply current
OH
min., though this cannot adversely
are recommended input voltages.
and V
are guaranteed output voltages
V
V
IL
CCINT
35% V
30% V
V
CCO
REF
REF
V, Max
0.8
0.7
powering up simultaneously.
– 0.05
– 0.1
lines for a successful
CCO
CCO
Commercial
Industrial
Description
V
65% V
50% V
V
CCINT
REF
REF
V, Min
Families".
2.0
1.7
+ 0.05
XC2S50E - XC2S300E
XC2S400E - XC2S600E
XC2S50E - XC2S300E
XC2S400E - XC2S600E
After PCN
Before PCN
After PCN
+ 0.1
is applied.
CCO
CCO
www.xilinx.com
V
IH
Spartan-IIE FPGA Family: DC and Switching Characteristics
V
(2)
(2)
CCO
(2)
V, Max
1.95
A maximum limit for I
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of I
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
standards meet their specifications. The selected standards
are tested at minimum V
currents shown. Other standards are sample tested.
3.6
2.7
3.6
3.6
+ 0.5
After PCN
Before
PCN
After PCN
Before
PCN
10% V
V, Max
V
0.4
0.4
0.4
0.4
0.6
(2)
(2)
OL
CCO
(2)
(2)
CCPO
CCINT
CCO
V
CCPO
90% V
Min
CCO
300
500
500
500
700
500
is not specified. Be careful when
V, Min
2
2
-
ramps from 0 to 1.8V.
V
with the respective I
2.4
1.9
(1)
OH
-
-
by limiting the supply current
– 0.4
XAPP450 "Power-On Current
CCO
Typ
±60
-
-
-
-
-
-
-
-
Note (2)
mA
I
24
12
40
36
OL
8
Max
50
-
-
-
-
-
-
-
-
OL
Note (2)
and I
–24
–12
Units
mA
I
–8
OH
mA
mA
mA
mA
mA
ms
μA
-
-
μs
A
OH
33