XC2S100E-6TQ144C Xilinx Inc, XC2S100E-6TQ144C Datasheet - Page 71

• Manufacturer Part Number: XC2S100E-6TQ144C
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S100E-6TQ144C

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 40960
• Number Of I /o: 102
• Number Of Gates: 100000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Case: TQFP144
• Dc: 05+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1206

FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Notes:
1.
2.
DS077-4 (2.3) June 18, 2008
Product Specification
I/O, L6P
I/O, L6N
I/O
I/O, L5P
I/O, L5N
I/O, L4P
I/O, L4N
I/O, L3P
I/O, L3N
I/O, L2P_YY
I/O, VREF
Bank 0,
L2N_YY
I/O, L1P_YY
I/O, L1N_YY
I/O, L0P_YY
I/O, L0N_YY
I/O
TCK
Function
Although designated with the _YY suffix in the XC2S50E,
XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these
differential pairs are not asynchronous in the XC2S400E.
There is no pair L37.
Pad Name
R
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Pin
C7
C6
D6
D5
C5
C4
B7
A6
B6
A5
B5
E6
B4
A4
A3
B3
A2
200E, 300E,
200E, 300E,
100E, 200E,
100E, 200E,
100E, 200E,
100E, 200E,
300E, 400E
300E, 400E
300E, 400E
300E, 400E
100E, 300E
100E, 300E
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
Async.
Output
Option
LVDS
400E
400E
All
All
All
All
All
All
-
-
-
150E, 200E,
XC2S100E,
300E, 400E
XC2S200E,
300E, 400E
Option
V
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
FT256 Differential Clock Pins
Additional FT256 Package Pins
VCCINT Pins
C3
E12
P3
VCCO Bank 0 Pins
E8
VCCO Bank 1 Pins
E9
VCCO Bank 2 Pins
G11
VCCO Bank 3 Pins
J11
VCCO Bank 4 Pins
L9
Clock
GCK0
GCK1
GCK2
GCK3
Bank
4
5
1
0
Spartan-IIE FPGA Family: Pinout Tables
C14
P14
H11
L10
J12
M5
F7
F9
Pin
B8
C8
T9
T8
M12
H12
F10
K11
P
M9
D4
F8
GCK0, I
GCK1, I
GCK2, I
GCK3, I
-
Name
D13
N4
-
-
-
-
-
-
Pin
R9
R8
A8
D8
N
I/O (DLL),
I/O (DLL),
I/O (DLL),
I/O (DLL),
Name
L52N
L52P
L8P
L8N
N13
E5
-
-
-
-
-
-
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