XC2S100E-6TQ144C Xilinx Inc, XC2S100E-6TQ144C Datasheet - Page 58

• Manufacturer Part Number: XC2S100E-6TQ144C
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S100E-6TQ144C

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 40960
• Number Of I /o: 102
• Number Of Gates: 100000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP
• Case: TQFP144
• Dc: 05+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1206

Spartan-IIE FPGA Family: Pinout Tables
Pinout Tables
The following device-specific pinout tables include all pack-
ages available for each Spartan-IIE device. They follow the
pad locations around the die. In the TQ144 package, all
VCCO pins must be connected to the same voltage.
TQ144 Pinouts (XC2S50E and XC2S100E)
58
GND
TMS
I/O
I/O
I/O, VREF
Bank 7
I/O
I/O, L27P
I/O, L27N
GND
I/O, L26P_YY
I/O, L26N_YY
I/O, VREF
Bank 7, L25P
I/O, L25N
I/O
I/O (IRDY)
GND
VCCO
I/O (TRDY)
VCCINT
I/O
I/O, L24P
I/O, VREF
Bank 6, L24N
I/O, L23P_YY
I/O, L23N_YY
GND
I/O, L22P
Function
Pad Name
Bank
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
-
-
-
-
-
-
-
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
Pin
P1
P2
P3
P4
P5
P6
P7
P8
P9
XC2S50E XC2S100E
XC2S50E
XC2S50E
XC2S50E
XC2S50E
XC2S50E
XC2S50E
Async.
Output
Option
LVDS
All
All
All
All
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Option
V
All
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
TQ144 Pinouts (XC2S50E and XC2S100E)
I/O, L22N
I/O
I/O, VREF
Bank 6
I/O
I/O, L21P_YY
I/O, L21N_YY
M1
GND
M0
VCCO
M2
I/O, L20N_YY
I/O, L20P_YY
I/O
I/O, VREF
Bank 5
I/O
I/O, L19N_YY
I/O, L19P_YY
GND
VCCINT
I/O, L18N_YY
I/O, L18P_YY
I/O, VREF
Bank 5
I/O (DLL), L17N
VCCINT
GCK1, I
VCCO
GND
GCK0, I
(Continued)
Function
Pad Name
Bank
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
4
-
-
-
-
-
-
-
-
-
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
Pin
DS077-4 (2.3) June 18, 2008
XC2S50E XC2S100E
Async.
Output
Option
LVDS
Product Specification
All
All
All
All
All
All
All
All
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
XC2S100E
Option
V
All
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R