XC2S100E-6PQG208C Xilinx Inc, XC2S100E-6PQG208C Datasheet - Page 36
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XC2S100E-6PQG208C
Manufacturer Part Number
XC2S100E-6PQG208C
Description
FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S100E-6PQG208C
Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
2700
Device Logic Units
600
Device System Gates
100000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
40960
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
40960
Number Of I /o
146
Number Of Gates
100000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Spartan-IIE FPGA Family: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
36
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
T
T
PSDLL
PSFD
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
For data input with different standards, adjust the setup time delay by the values shown in
Standards, page
Global Clock Input Adjustments, page
A zero hold time listing indicates no hold time or a negative hold time.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
For data input with different standards, adjust the setup time delay by the values shown in
Standards, page
Global Clock Input Adjustments, page
Symbol
Symbol
/ T
/ T
PHDLL
PHFD
38. For a global clock input with standards other than LVTTL, adjust delays with values from the
38. For a global clock input with standards other than LVTTL, adjust delays with values from the
Input setup and hold time relative to global clock input signal
for LVTTL standard, no delay, IFF,
Input setup and hold time relative
to global clock input signal for
LVTTL standard, with delay, IFF,
without DLL
Description
42.
42.
Description
(1)
www.xilinx.com
(1)
with DLL
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
Device
IOB Input Delay Adjustments for Different
IOB Input Delay Adjustments for Different
1.6 / 0
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
Min
Min
-7
-7
Speed Grade
Speed Grade
DS077-3 (v2.3) June 18, 2008
Product Specification
1.7 / 0
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
Min
Min
-6
-6
I/O Standard
I/O Standard
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
R