XC2C384-7FTG256C Xilinx Inc, XC2C384-7FTG256C Datasheet - Page 8

• Manufacturer Part Number: XC2C384-7FTG256C
• Description: CPLD CoolRunner™-II Family 9K Gates 384 Macro Cells 217MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C384-7FTG256C

• Package: 256FTBGA
• Family Name: CoolRunner™-II
• Device System Gates: 9000
• Number Of Macro Cells: 384
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 212
• Number Of Logic Blocks/elements: 24
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 217 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.1ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 24
• Number Of Macrocells: 384
• Number Of Gates: 9000
• Number Of I /o: 212
• Mounting Type: Surface Mount
• Package / Case: 256-FTBGA
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1414

XC2C384 CoolRunner-II CPLD
Internal Timing Parameters
8
Buffer Delays
T
T
T
T
T
T
T
P-term Delays
T
T
T
Macrocell Delay
T
T
T
T
T
T
T
T
Feedback Delays
T
T
I/O Standard Time Adder Delays 1.5V CMOS
T
T
T
I/O Standard Time Adder Delays 1.8V CMOS
T
T
T
I/O Standard Time Adder Delays 2.5V CMOS
T
T
T
T
OUT
AOI
OEM
OUT15
OUT18
OUT25
IN
DIN
GCK
GSR
GTS
EN
CT
LOGI1
LOGI2
PDI
SUI
HI
ECSU
ECHO
COI
CDBL
F
HYS15
SLEW15
HYS18
SLEW
IN25
HYS25
SLEW25
Symbol
Input buffer delay
Direct data register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
Control term delay
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
Setup before clock
Hold after clock
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Clock doubler delay
Feedback delay
Macrocell to global OE delay
Hysteresis input adder
Output adder
Output slew rate adder
Hysteresis input adder
Output adder
Output slew rate adder
Standard input adder
Hysteresis input adder
Output adder
Output slew rate adder
Parameter
(1)
www.xilinx.com
Min.
1.7
0.0
1.5
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
3.1
4.5
2.1
2.4
2.9
3.0
3.1
0.8
0.5
0.4
0.5
0.2
0.6
2.2
2.6
3.0
0.8
4.0
2.0
0.0
2.0
0.6
1.5
0.8
3.0
0
-
-
-
-
Min.
2.0
0.0
2.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS095 (v3.2) March 8, 2007
-10
Product Specification
Max.
3.8
5.5
3.3
4.6
3.7
3.9
5.5
0.9
0.8
0.8
0.7
0.7
3.0
4.5
3.0
4.0
1.0
4.0
4.0
0.0
4.0
1.0
3.0
3.0
4.0
0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R