XA2C256-8VQG100Q Xilinx Inc, XA2C256-8VQG100Q Datasheet - Page 7
![CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 139MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XA2C256-8VQG100Q
Manufacturer Part Number
XA2C256-8VQG100Q
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 139MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheet
1.XA2C256-7VQG100I.pdf
(19 pages)
Specifications of XA2C256-8VQG100Q
Package
100VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
80
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
139 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 105 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
80
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA2C256-8VQG100Q
Manufacturer:
XILINX
Quantity:
210
(
Internal Timing Parameters
DS555 (v1.2) June 22, 2009
Product Specification
Buffer Delays
T
T
T
T
T
T
T
P-term Delays
T
T
T
Macrocell Delay
T
T
T
T
T
T
T
T
Feedback Delays
T
T
I/O Standard Time Adder Delays 1.5V CMOS
T
T
T
I/O Standard Time Adder Delays 1.8V CMOS
T
T
T
AOI
OUT
OEM
OUT15
OUT18
IN
DIN
GCK
GSR
GTS
EN
CT
LOGI1
LOGI2
PDI
LDI
SUI
HI
ECSU
ECHO
COI
F
HYS15
SLEW15
HYS18
SLEW
Symbol
R
Input buffer delay
Direct data register input delay
Global Clock buffer delay
Global set/reset buffer delay
Global 3-state buffer delay
Output buffer delay
Output buffer enable/disable delay
Control term delay
Single P-term delay adder
Multiple P-term delay adder
Input to output valid
Setup before clock (transparent latch)
Setup before clock
Hold after clock
Enable clock setup time
Enable clock hold time
Clock to output valid
Set/reset to output valid
Feedback delay
Macrocell to global OE delay
Hysteresis input adder
Output adder
Output slew rate adder
Hysteresis input adder
Output adder
Output slew rate adder
Parameter
(2)
www.xilinx.com
Min.
1.8
0.0
1.8
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
XA2C256 CoolRunner-II Automotive CPLD
Max.
0.5
2.6
3.9
2.7
3.5
3.0
2.6
4.0
1.4
1.1
0.7
2.5
0.7
1.5
3.0
2.5
4.0
1.0
5.0
3.0
0.0
4.0
-
-
-
-
Min.
2.4
0.0
1.1
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-8
Max.
2.6
2.7
4.1
3.0
2.6
4.0
2.5
1.1
0.5
0.7
0.7
0.9
3.0
2.5
1.0
5.0
0.0
4.0
3.3
2.5
4.0
3.0
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7