XA2C256-8VQG100Q Xilinx Inc, XA2C256-8VQG100Q Datasheet - Page 13
![CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 139MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XA2C256-8VQG100Q
Manufacturer Part Number
XA2C256-8VQG100Q
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 139MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheet
1.XA2C256-7VQG100I.pdf
(19 pages)
Specifications of XA2C256-8VQG100Q
Package
100VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
80
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
139 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 105 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
80
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XA2C256-8VQG100Q
Manufacturer:
XILINX
Quantity:
210
Pin Descriptions (Continued)
DS555 (v1.2) June 22, 2009
Product Specification
Function Block
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
R
Macro-
cell
10
11
12
13
14
15
16
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VQG100
53
54
55
56
52
50
49
46
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TQG144
75
76
77
78
79
80
81
82
74
71
70
69
68
66
64
61
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
Pin Descriptions (Continued)
Notes:
1.
2.
Function Block
GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
GTS, GSR and GCK pins can be used for general purpose
I/O.
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
XA2C256 CoolRunner-II Automotive CPLD
Macro-
cell
10
11
12
13
14
15
16
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VQG100
58
59
60
61
63
64
43
42
41
40
39
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TQG144
83
85
86
87
88
91
92
60
59
58
57
56
54
53
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
13