LCMXO1200C-3TN144C LATTICE SEMICONDUCTOR, LCMXO1200C-3TN144C Datasheet - Page 81

• Manufacturer Part Number: LCMXO1200C-3TN144C
• Description: CPLD MachXO Family 600 Macro Cells 1.8V/2.5V/3.3V 144-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LCMXO1200C-3TN144C

• Package: 144TQFP
• Family Name: MachXO
• Number Of Macro Cells: 600
• Maximum Propagation Delay Time: 5.1 ns
• Number Of User I/os: 113
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Ram Bits: 9420.8
• Memory Type: SRAM
• Operating Temperature: 0 to 85 °C

Lattice Semiconductor
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following:
•
• TN1090 -
• Power Calculator tool included with the Lattice ispLEVER design tool, or as a standalone download from 
Thermal Management
www.latticesemi.com/software
Power Estimation and Management for MachXO Devices
document
Thermal Management
4-36
document to find the device/package
MachXO Family Data Sheet
Pinout Information