ZY7015L-T3 POWER ONE, ZY7015L-T3 Datasheet - Page 26

• Manufacturer Part Number: ZY7015L-T3
• Description: Module DC-DC 1-OUT 0.5V to 5.5V 15A 25-Pin SMT T/R
• Manufacturer: POWER ONE
• Type: Step Downr

Specifications of ZY7015L-T3

• Package: 25SMT
• Output Current: 15 A
• Output Voltage: 0.5 to 5.5 V
• Input Voltage: 3 to 13.2 V
• Number Of Outputs: 1
• Switching Regulator: Yes

8.4
Z-Series POLs utilize the digital PWM controller.
The controller enables users to program most of the
PWM performance parameters, such as switching
frequency, interleave, duty cycle, and feedback loop
compensation.
8.4.1
The switching frequency can be programmed in the
GUI PWM Controller window shown in Figure 47 or
directly via the I
shown in Figure 48. Note that the content of the
register can be changed only when the POL is
turned off.
Switching actions of all POLs connected to the SD
line are synchronized to the master clock generated
by the DPM. Each POL is equipped with a PLL and
a frequency divider so they can operate at multiples
(including fractional) of the master clock frequency
as programmed by a user. The POL converters can
operate at 500 kHz, 750 kHz, and 1 MHz. Although
synchronized, switching frequencies of different
POLs are independent of each other.
permissible to mix POLs operating at different
frequencies in one system.
efficiency and transient response of each POL in the
system individually.
ZD-00283 Rev. 2.5, 01-Jul-10
PWM Parameters
Switching Frequency
Figure 47. PWM Controller Window
2
C bus by writing into the INT register
It allows optimizing
www.power-one.com
ZY7015 15A DC-DC Intelligent POL Data Sheet
It is
3V to 13.2V Input
8.4.2
Interleave is defined as a phase delay between the
synchronizing slope of the master clock on the SD
pin and PWM signal of a POL. The interleave can
be programmed in the GUI PWM Controller window
or directly via the I
register.
Every POL generates switching noise.
interleave is programmed, all POLs in the system
switch simultaneously and noise reflected to the
input source from all POLs is added together as
shown in Figure 49.
Bit 7:5 FRQ[2:0] : PWM Frequency Selection
Bit 4:0 INT[4:0] : Interleave position
1)
R/W-0
Initial value depends on the state of the Interleave Mode ( IM) Input:
FRQ2
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded
IM=Low:
Bit 7
Figure 48. Interleave Configuration Register INT
Figure 49. Input Voltage Noise, No Interleave
000: 500kHz
001: 750kHz
010: 1000lHz
011: 1250kHz
100: 1250kHz
101: 1500kHz
110: 1750kHz
111: 2000kHz
00h: Ton starts with 0.0° Phase lag to SD Line
01h: Ton starts wi th 11.25° Phase lag to SD Line
02h: Ton starts with 22.50° Phase lag to SD Line
…
1Fh: Ton starts with 348.75° Phase lag to SD Line
Interleave
R/W-0
FRQ1
At POR reset a 0 is loaded
R/W-0
FRQ0
2
C bus by writing into the INT

R/W-0
INT4
0.5V to 5.5V Output
1)
R/W-0
INT3
1)
Page 26 of 34
R/W-0
INT2
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1)
read as ‘0’
R/W-0
INT1
1)
R/W-0
If no
INT0
Bit 0
1)